mirror of
https://github.com/hrydgard/ppsspp.git
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130 lines
3.3 KiB
C++
130 lines
3.3 KiB
C++
// Copyright (c) 2012- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#pragma once
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#include "../MIPS.h"
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#include "../MIPSAnalyst.h"
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#include "ArmEmitter.h"
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using namespace ArmGen;
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#define CTXREG (R10)
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// R2 to R8: mapped MIPS regs
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// R9 = code pointers
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// R10 = MIPS context
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// R11 = base pointer
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// Special MIPS registers:
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enum {
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MIPSREG_HI = 32,
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MIPSREG_LO = 33,
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TOTAL_MAPPABLE_MIPSREGS = 34,
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};
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typedef int MIPSReg;
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struct RegARM {
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int mipsReg; // if -1, no mipsreg attached.
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bool isDirty; // Should the register be written back?
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};
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enum RegMIPSLoc {
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ML_IMM,
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ML_ARMREG,
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ML_MEM,
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};
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struct RegMIPS {
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// Where is this MIPS register?
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RegMIPSLoc loc;
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// Data (only one of these is used, depending on loc. Could make a union).
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u32 imm;
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ARMReg reg; // reg index
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bool spillLock; // if true, this register cannot be spilled.
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// If loc == ML_MEM, it's back in its location in the CPU context struct.
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};
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#undef MAP_DIRTY
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#undef MAP_NOINIT
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// Initing is the default so the flag is reversed.
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enum {
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MAP_DIRTY = 1,
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MAP_NOINIT = 2,
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};
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namespace MIPSComp {
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struct ArmJitOptions;
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}
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class ArmRegCache
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{
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public:
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ArmRegCache(MIPSState *mips, MIPSComp::ArmJitOptions *options);
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~ArmRegCache() {}
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void Init(ARMXEmitter *emitter);
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void Start(MIPSAnalyst::AnalysisResults &stats);
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// Protect the arm register containing a MIPS register from spilling, to ensure that
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// it's being kept allocated.
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void SpillLock(MIPSReg reg, MIPSReg reg2 = -1, MIPSReg reg3 = -1, MIPSReg reg4 = -1);
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void ReleaseSpillLock(MIPSReg reg);
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void ReleaseSpillLocks();
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void SetImm(MIPSReg reg, u32 immVal);
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bool IsImm(MIPSReg reg) const;
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u32 GetImm(MIPSReg reg) const;
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// Returns an ARM register containing the requested MIPS register.
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ARMReg MapReg(MIPSReg reg, int mapFlags = 0);
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void MapInIn(MIPSReg rd, MIPSReg rs);
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void MapDirtyIn(MIPSReg rd, MIPSReg rs, bool avoidLoad = true);
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void MapDirtyInIn(MIPSReg rd, MIPSReg rs, MIPSReg rt, bool avoidLoad = true);
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void MapDirtyDirtyInIn(MIPSReg rd1, MIPSReg rd2, MIPSReg rs, MIPSReg rt, bool avoidLoad = true);
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void FlushArmReg(ARMReg r);
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void FlushR(MIPSReg r);
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void FlushBeforeCall();
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void FlushAll();
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void DiscardR(MIPSReg r);
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ARMReg R(int preg); // Returns a cached register
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void SetEmitter(ARMXEmitter *emitter) { emit_ = emitter; }
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// For better log output only.
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void SetCompilerPC(u32 compilerPC) { compilerPC_ = compilerPC; }
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int GetMipsRegOffset(MIPSReg r);
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private:
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const ARMReg *GetMIPSAllocationOrder(int &count);
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MIPSState *mips_;
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MIPSComp::ArmJitOptions *options_;
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ARMXEmitter *emit_;
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u32 compilerPC_;
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enum {
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NUM_ARMREG = 16,
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NUM_MIPSREG = TOTAL_MAPPABLE_MIPSREGS,
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};
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RegARM ar[NUM_ARMREG];
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RegMIPS mr[NUM_MIPSREG];
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};
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