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https://github.com/hrydgard/ppsspp.git
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583927988c
Implement vsat0 and vsat1 Introduce VMOV for immediates. Use in MOVI2F where possible by detecting if float val can be encoded. Combine some vneg ops in ApplyPrefixST.
762 lines
18 KiB
C++
762 lines
18 KiB
C++
// Copyright (c) 2012- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include "../../MemMap.h"
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#include "../MIPSAnalyst.h"
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#include "Common/CPUDetect.h"
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#include "Core/Config.h"
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#include "Core/Reporting.h"
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#include "ArmJit.h"
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#include "ArmRegCache.h"
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#define _RS ((op>>21) & 0x1F)
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#define _RT ((op>>16) & 0x1F)
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#define _RD ((op>>11) & 0x1F)
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#define _FS ((op>>11) & 0x1F)
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#define _FT ((op>>16) & 0x1F)
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#define _FD ((op>>6 ) & 0x1F)
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#define _POS ((op>>6 ) & 0x1F)
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#define _SIZE ((op>>11 ) & 0x1F)
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// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly.
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// Currently known non working ones should have DISABLE.
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// #define CONDITIONAL_DISABLE { fpr.ReleaseSpillLocks(); Comp_Generic(op); return; }
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#define CONDITIONAL_DISABLE ;
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#define DISABLE { fpr.ReleaseSpillLocks(); Comp_Generic(op); return; }
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namespace MIPSComp
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{
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// Vector regs can overlap in all sorts of swizzled ways.
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// This does allow a single overlap in sregs[i].
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bool IsOverlapSafeAllowS(int dreg, int di, int sn, u8 sregs[], int tn = 0, u8 tregs[] = NULL)
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{
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for (int i = 0; i < sn; ++i)
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{
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if (sregs[i] == dreg && i != di)
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return false;
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}
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for (int i = 0; i < tn; ++i)
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{
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if (tregs[i] == dreg)
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return false;
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}
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// Hurray, no overlap, we can write directly.
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return true;
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}
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bool IsOverlapSafe(int dreg, int di, int sn, u8 sregs[], int tn = 0, u8 tregs[] = NULL)
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{
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return IsOverlapSafeAllowS(dreg, di, sn, sregs, tn, tregs) && sregs[di] != dreg;
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}
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void Jit::Comp_VPFX(u32 op)
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{
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CONDITIONAL_DISABLE;
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int data = op & 0xFFFFF;
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int regnum = (op >> 24) & 3;
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switch (regnum) {
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case 0: // S
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js.prefixS = data;
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js.prefixSFlag = ArmJitState::PREFIX_KNOWN_DIRTY;
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break;
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case 1: // T
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js.prefixT = data;
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js.prefixTFlag = ArmJitState::PREFIX_KNOWN_DIRTY;
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break;
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case 2: // D
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js.prefixD = data;
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js.prefixDFlag = ArmJitState::PREFIX_KNOWN_DIRTY;
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break;
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}
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}
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void Jit::ApplyPrefixST(u8 *vregs, u32 prefix, VectorSize sz) {
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if (prefix == 0xE4) return;
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int n = GetNumVectorElements(sz);
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u8 origV[4];
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static const float constantArray[8] = {0.f, 1.f, 2.f, 0.5f, 3.f, 1.f/3.f, 0.25f, 1.f/6.f};
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for (int i = 0; i < n; i++)
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origV[i] = vregs[i];
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for (int i = 0; i < n; i++)
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{
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int regnum = (prefix >> (i*2)) & 3;
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int abs = (prefix >> (8+i)) & 1;
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int negate = (prefix >> (16+i)) & 1;
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int constants = (prefix >> (12+i)) & 1;
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// Unchanged, hurray.
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if (!constants && regnum == i && !abs && !negate)
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continue;
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// This puts the value into a temp reg, so we won't write the modified value back.
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vregs[i] = fpr.GetTempV();
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fpr.MapRegV(vregs[i], MAP_NOINIT | MAP_DIRTY);
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if (!constants) {
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// Prefix may say "z, z, z, z" but if this is a pair, we force to x.
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// TODO: But some ops seem to use const 0 instead?
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if (regnum >= n) {
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ERROR_LOG_REPORT(CPU, "Invalid VFPU swizzle: %08x / %d", prefix, sz);
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regnum = 0;
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}
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if (abs) {
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VABS(fpr.V(vregs[i]), fpr.V(origV[regnum]));
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if (negate)
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VNEG(fpr.V(vregs[i]), fpr.V(vregs[i]));
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} else {
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if (negate)
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VNEG(fpr.V(vregs[i]), fpr.V(origV[regnum]));
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else
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VMOV(fpr.V(vregs[i]), fpr.V(origV[regnum]));
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}
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} else {
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MOVI2F(fpr.V(vregs[i]), constantArray[regnum + (abs<<2)], R0, negate);
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}
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// TODO: This probably means it will swap out soon, inefficiently...
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fpr.ReleaseSpillLockV(vregs[i]);
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}
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}
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void Jit::GetVectorRegsPrefixD(u8 *regs, VectorSize sz, int vectorReg) {
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_assert_(js.prefixDFlag & ArmJitState::PREFIX_KNOWN);
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GetVectorRegs(regs, sz, vectorReg);
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if (js.prefixD == 0)
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return;
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int n = GetNumVectorElements(sz);
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for (int i = 0; i < n; i++) {
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// Hopefully this is rare, we'll just write it into a reg we drop.
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if (js.VfpuWriteMask(i))
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regs[i] = fpr.GetTempV();
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}
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}
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void Jit::ApplyPrefixD(const u8 *vregs, VectorSize sz) {
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_assert_(js.prefixDFlag & ArmJitState::PREFIX_KNOWN);
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if (!js.prefixD) return;
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int n = GetNumVectorElements(sz);
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for (int i = 0; i < n; i++) {
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if (js.VfpuWriteMask(i))
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continue;
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int sat = (js.prefixD >> (i * 2)) & 3;
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if (sat == 1) {
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// clamped = fabs(x) - fabs(x-0.5f) + 0.5f; // [ 0, 1]
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fpr.MapRegV(vregs[i], MAP_DIRTY);
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MOVI2F(S0, 0.5f, R0);
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VABS(S1, fpr.V(vregs[i])); // S1 = fabs(x)
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VSUB(S2, fpr.V(vregs[i]), S0); // S2 = fabs(x-0.5f) {VABD}
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VABS(S2, S2);
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VSUB(fpr.V(vregs[i]), S1, S2); // v[i] = S1 - S2 + 0.5f
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VADD(fpr.V(vregs[i]), fpr.V(vregs[i]), S0);
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} else if (sat == 3) {
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// clamped = fabs(x) - fabs(x-1.0f); // [-1, 1]
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fpr.MapRegV(vregs[i], MAP_DIRTY);
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MOVI2F(S0, 1.0f, R0);
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VABS(S1, fpr.V(vregs[i])); // S1 = fabs(x)
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VSUB(S2, fpr.V(vregs[i]), S0); // S2 = fabs(x-1.0f) {VABD}
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VABS(S2, S2);
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VSUB(fpr.V(vregs[i]), S1, S2); // v[i] = S1 - S2
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}
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}
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}
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void Jit::Comp_SV(u32 op) {
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CONDITIONAL_DISABLE;
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s32 imm = (signed short)(op&0xFFFC);
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int vt = ((op >> 16) & 0x1f) | ((op & 3) << 5);
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int rs = _RS;
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bool doCheck = false;
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switch (op >> 26)
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{
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case 50: //lv.s // VI(vt) = Memory::Read_U32(addr);
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{
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// CC might be set by slow path below, so load regs first.
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fpr.MapRegV(vt, MAP_DIRTY | MAP_NOINIT);
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fpr.ReleaseSpillLocks();
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if (gpr.IsImm(rs)) {
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u32 addr = (imm + gpr.GetImm(rs)) & 0x3FFFFFFF;
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MOVI2R(R0, addr + (u32)Memory::base);
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} else {
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gpr.MapReg(rs);
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if (g_Config.bFastMemory) {
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SetR0ToEffectiveAddress(rs, imm);
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} else {
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SetCCAndR0ForSafeAddress(rs, imm, R1);
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doCheck = true;
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}
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ADD(R0, R0, R11);
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}
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VLDR(fpr.V(vt), R0, 0);
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if (doCheck) {
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SetCC(CC_EQ);
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MOVI2F(fpr.V(vt), 0.0f, R0);
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SetCC(CC_AL);
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}
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}
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break;
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case 58: //sv.s // Memory::Write_U32(VI(vt), addr);
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{
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// CC might be set by slow path below, so load regs first.
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fpr.MapRegV(vt);
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fpr.ReleaseSpillLocks();
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if (gpr.IsImm(rs)) {
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u32 addr = (imm + gpr.GetImm(rs)) & 0x3FFFFFFF;
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MOVI2R(R0, addr + (u32)Memory::base);
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} else {
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gpr.MapReg(rs);
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if (g_Config.bFastMemory) {
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SetR0ToEffectiveAddress(rs, imm);
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} else {
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SetCCAndR0ForSafeAddress(rs, imm, R1);
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doCheck = true;
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}
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ADD(R0, R0, R11);
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}
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VSTR(fpr.V(vt), R0, 0);
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if (doCheck) {
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SetCC(CC_AL);
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}
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}
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break;
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default:
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DISABLE;
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}
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}
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void Jit::Comp_SVQ(u32 op)
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{
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CONDITIONAL_DISABLE;
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int imm = (signed short)(op&0xFFFC);
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int vt = (((op >> 16) & 0x1f)) | ((op&1) << 5);
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int rs = _RS;
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bool doCheck = false;
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switch (op >> 26)
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{
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case 54: //lv.q
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{
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// CC might be set by slow path below, so load regs first.
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u8 vregs[4];
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GetVectorRegs(vregs, V_Quad, vt);
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fpr.MapRegsV(vregs, V_Quad, MAP_DIRTY | MAP_NOINIT);
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fpr.ReleaseSpillLocks();
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if (gpr.IsImm(rs)) {
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u32 addr = (imm + gpr.GetImm(rs)) & 0x3FFFFFFF;
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MOVI2R(R0, addr + (u32)Memory::base);
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} else {
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gpr.MapReg(rs);
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if (g_Config.bFastMemory) {
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SetR0ToEffectiveAddress(rs, imm);
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} else {
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SetCCAndR0ForSafeAddress(rs, imm, R1);
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doCheck = true;
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}
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ADD(R0, R0, R11);
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}
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for (int i = 0; i < 4; i++)
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VLDR(fpr.V(vregs[i]), R0, i * 4);
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if (doCheck) {
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SetCC(CC_EQ);
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MOVI2R(R0, 0);
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for (int i = 0; i < 4; i++)
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VMOV(fpr.V(vregs[i]), R0);
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SetCC(CC_AL);
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}
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}
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break;
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case 62: //sv.q
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{
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// CC might be set by slow path below, so load regs first.
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u8 vregs[4];
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GetVectorRegs(vregs, V_Quad, vt);
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fpr.MapRegsV(vregs, V_Quad, 0);
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fpr.ReleaseSpillLocks();
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if (gpr.IsImm(rs)) {
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u32 addr = (imm + gpr.GetImm(rs)) & 0x3FFFFFFF;
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MOVI2R(R0, addr + (u32)Memory::base);
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} else {
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gpr.MapReg(rs);
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if (g_Config.bFastMemory) {
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SetR0ToEffectiveAddress(rs, imm);
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} else {
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SetCCAndR0ForSafeAddress(rs, imm, R1);
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doCheck = true;
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}
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ADD(R0, R0, R11);
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}
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for (int i = 0; i < 4; i++)
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VSTR(fpr.V(vregs[i]), R0, i * 4);
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if (doCheck) {
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SetCC(CC_AL);
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}
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}
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break;
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default:
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DISABLE;
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break;
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}
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}
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void Jit::Comp_VVectorInit(u32 op)
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{
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CONDITIONAL_DISABLE;
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// WARNING: No prefix support!
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if (js.MayHavePrefix()) {
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Comp_Generic(op);
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js.EatPrefix();
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return;
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}
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switch ((op >> 16) & 0xF)
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{
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case 6: // v=zeros; break; //vzero
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MOVI2F(S0, 0.0f, R0);
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break;
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case 7: // v=ones; break; //vone
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MOVI2F(S0, 1.0f, R0);
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break;
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default:
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DISABLE;
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break;
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}
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VectorSize sz = GetVecSize(op);
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int n = GetNumVectorElements(sz);
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u8 dregs[4];
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GetVectorRegsPrefixD(dregs, sz, _VD);
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fpr.MapRegsV(dregs, sz, MAP_NOINIT | MAP_DIRTY);
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for (int i = 0; i < n; ++i)
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VMOV(fpr.V(dregs[i]), S0);
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ApplyPrefixD(dregs, sz);
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fpr.ReleaseSpillLocks();
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}
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void Jit::Comp_VDot(u32 op)
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{
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// DISABLE;
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CONDITIONAL_DISABLE;
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// WARNING: No prefix support!
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if (js.MayHavePrefix()) {
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Comp_Generic(op);
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js.EatPrefix();
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return;
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}
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int vd = _VD;
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int vs = _VS;
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int vt = _VT;
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VectorSize sz = GetVecSize(op);
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// TODO: Force read one of them into regs? probably not.
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u8 sregs[4], tregs[4];
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GetVectorRegs(sregs, sz, vs);
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GetVectorRegs(tregs, sz, vt);
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// TODO: applyprefixST here somehow (shuffle, etc...)
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fpr.MapRegsV(sregs, sz, 0);
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fpr.MapRegsV(tregs, sz, 0);
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VMUL(S0, fpr.V(sregs[0]), fpr.V(tregs[0]));
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int n = GetNumVectorElements(sz);
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for (int i = 1; i < n; i++) {
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// sum += s[i]*t[i];
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VMLA(S0, fpr.V(sregs[i]), fpr.V(tregs[i]));
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}
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fpr.ReleaseSpillLocks();
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fpr.MapRegV(vd, MAP_NOINIT | MAP_DIRTY);
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// TODO: applyprefixD here somehow (write mask etc..)
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VMOV(fpr.V(vd), S0);
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fpr.ReleaseSpillLocks();
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js.EatPrefix();
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}
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void Jit::Comp_VecDo3(u32 op)
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{
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CONDITIONAL_DISABLE;
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DISABLE;
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// WARNING: No prefix support!
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if (js.MayHavePrefix())
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{
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Comp_Generic(op);
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js.EatPrefix();
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return;
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}
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int vd = _VD;
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int vs = _VS;
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int vt = _VT;
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void (ARMXEmitter::*triop)(ARMReg, ARMReg, ARMReg) = NULL;
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switch (op >> 26)
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{
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case 24: //VFPU0
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switch ((op >> 23)&7)
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{
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case 0: // d[i] = s[i] + t[i]; break; //vadd
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triop = &ARMXEmitter::VADD;
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break;
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case 1: // d[i] = s[i] - t[i]; break; //vsub
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triop = &ARMXEmitter::VSUB;
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break;
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case 7: // d[i] = s[i] / t[i]; break; //vdiv
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triop = &ARMXEmitter::VDIV;
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break;
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}
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break;
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case 25: //VFPU1
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switch ((op >> 23)&7)
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{
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case 0: // d[i] = s[i] * t[i]; break; //vmul
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triop = &ARMXEmitter::VMUL;
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break;
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}
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break;
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}
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if (!triop) {
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DISABLE;
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}
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VectorSize sz = GetVecSize(op);
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int n = GetNumVectorElements(sz);
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u8 sregs[4], tregs[4], dregs[4];
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GetVectorRegsPrefixS(sregs, sz, _VS);
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GetVectorRegsPrefixT(tregs, sz, _VT);
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GetVectorRegsPrefixD(dregs, sz, _VD);
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MIPSReg tempregs[4];
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for (int i = 0; i < n; i++) {
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if (!IsOverlapSafeAllowS(dregs[i], i, n, sregs, n, tregs)) {
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tempregs[i] = fpr.GetTempV();
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} else {
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fpr.MapRegV(dregs[i], (dregs[i] == sregs[i] || dregs[i] == tregs[i] ? 0 : MAP_NOINIT) | MAP_DIRTY);
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tempregs[i] = dregs[i];
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}
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}
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for (int i = 0; i < n; i++) {
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fpr.SpillLockV(sregs[i]);
|
|
fpr.SpillLockV(tregs[i]);
|
|
fpr.MapRegV(sregs[i]);
|
|
fpr.MapRegV(tregs[i]);
|
|
fpr.MapRegV(tempregs[i]);
|
|
(this->*triop)(fpr.V(tempregs[i]), fpr.V(sregs[i]), fpr.V(tregs[i]));
|
|
fpr.ReleaseSpillLockV(sregs[i]);
|
|
fpr.ReleaseSpillLockV(tregs[i]);
|
|
}
|
|
|
|
fpr.MapRegsV(dregs, sz, MAP_DIRTY);
|
|
for (int i = 0; i < n; i++) {
|
|
if (dregs[i] != tempregs[i])
|
|
VMOV(fpr.V(dregs[i]), fpr.V(tempregs[i]));
|
|
}
|
|
ApplyPrefixD(dregs, sz);
|
|
|
|
fpr.ReleaseSpillLocks();
|
|
|
|
js.EatPrefix();
|
|
}
|
|
|
|
void Jit::Comp_VV2Op(u32 op) {
|
|
CONDITIONAL_DISABLE;
|
|
|
|
DISABLE;
|
|
|
|
if (js.HasUnknownPrefix())
|
|
DISABLE;
|
|
|
|
VectorSize sz = GetVecSize(op);
|
|
int n = GetNumVectorElements(sz);
|
|
|
|
u8 sregs[4], dregs[4];
|
|
GetVectorRegsPrefixS(sregs, sz, _VS);
|
|
GetVectorRegsPrefixD(dregs, sz, _VD);
|
|
|
|
ARMReg tempxregs[4];
|
|
for (int i = 0; i < n; ++i)
|
|
{
|
|
if (!IsOverlapSafeAllowS(dregs[i], i, n, sregs))
|
|
{
|
|
int reg = fpr.GetTempV();
|
|
fpr.MapRegV(reg, MAP_NOINIT | MAP_DIRTY);
|
|
fpr.SpillLockV(reg);
|
|
tempxregs[i] = fpr.V(reg);
|
|
}
|
|
else
|
|
{
|
|
fpr.MapRegV(dregs[i], (dregs[i] == sregs[i] ? 0 : MAP_NOINIT) | MAP_DIRTY);
|
|
fpr.SpillLockV(dregs[i]);
|
|
tempxregs[i] = fpr.V(dregs[i]);
|
|
}
|
|
}
|
|
|
|
// Warning: sregs[i] and tempxregs[i] may be the same reg.
|
|
// Helps for vmov, hurts for vrcp, etc.
|
|
for (int i = 0; i < n; ++i)
|
|
{
|
|
switch ((op >> 16) & 0x1f)
|
|
{
|
|
case 0: // d[i] = s[i]; break; //vmov
|
|
// Probably for swizzle.
|
|
VMOV(tempxregs[i], fpr.V(sregs[i]));
|
|
break;
|
|
case 1: // d[i] = fabsf(s[i]); break; //vabs
|
|
//if (!fpr.V(sregs[i]).IsSimpleReg(tempxregs[i]))
|
|
VABS(tempxregs[i], fpr.V(sregs[i]));
|
|
break;
|
|
case 2: // d[i] = -s[i]; break; //vneg
|
|
VNEG(tempxregs[i], fpr.V(sregs[i]));
|
|
break;
|
|
case 4: // if (s[i] < 0) d[i] = 0; else {if(s[i] > 1.0f) d[i] = 1.0f; else d[i] = s[i];} break; // vsat0
|
|
MOVI2F(S0, 0.5f, R0);
|
|
VABS(S1, fpr.V(sregs[i])); // S1 = fabs(x)
|
|
VSUB(S2, fpr.V(sregs[i]), S0); // S2 = fabs(x-0.5f) {VABD}
|
|
VABS(S2, S2);
|
|
VSUB(fpr.V(tempxregs[i]), S1, S2); // v[i] = S1 - S2 + 0.5f
|
|
VADD(fpr.V(tempxregs[i]), fpr.V(tempxregs[i]), S0);
|
|
break;
|
|
case 5: // if (s[i] < -1.0f) d[i] = -1.0f; else {if(s[i] > 1.0f) d[i] = 1.0f; else d[i] = s[i];} break; // vsat1
|
|
MOVI2F(S0, 1.0f, R0);
|
|
VABS(S1, fpr.V(sregs[i])); // S1 = fabs(x)
|
|
VSUB(S2, fpr.V(sregs[i]), S0); // S2 = fabs(x-1.0f) {VABD}
|
|
VABS(S2, S2);
|
|
VSUB(fpr.V(tempxregs[i]), S1, S2); // v[i] = S1 - S2
|
|
break;
|
|
case 16: // d[i] = 1.0f / s[i]; break; //vrcp
|
|
MOVI2F(S0, 1.0f, R0);
|
|
VDIV(tempxregs[i], S0, fpr.V(sregs[i]));
|
|
break;
|
|
case 17: // d[i] = 1.0f / sqrtf(s[i]); break; //vrsq
|
|
MOVI2F(S0, 1.0f, R0);
|
|
VSQRT(S1, fpr.V(sregs[i]));
|
|
VDIV(tempxregs[i], S0, S1);
|
|
break;
|
|
case 18: // d[i] = sinf((float)M_PI_2 * s[i]); break; //vsin
|
|
DISABLE;
|
|
break;
|
|
case 19: // d[i] = cosf((float)M_PI_2 * s[i]); break; //vcos
|
|
DISABLE;
|
|
break;
|
|
case 20: // d[i] = powf(2.0f, s[i]); break; //vexp2
|
|
DISABLE;
|
|
break;
|
|
case 21: // d[i] = logf(s[i])/log(2.0f); break; //vlog2
|
|
DISABLE;
|
|
break;
|
|
case 22: // d[i] = sqrtf(s[i]); break; //vsqrt
|
|
VSQRT(tempxregs[i], fpr.V(sregs[i]));
|
|
VABS(tempxregs[i], tempxregs[i]);
|
|
break;
|
|
case 23: // d[i] = asinf(s[i] * (float)M_2_PI); break; //vasin
|
|
DISABLE;
|
|
break;
|
|
case 24: // d[i] = -1.0f / s[i]; break; // vnrcp
|
|
MOVI2F(S0, -1.0f, R0);
|
|
VDIV(tempxregs[i], S0, fpr.V(sregs[i]));
|
|
break;
|
|
case 26: // d[i] = -sinf((float)M_PI_2 * s[i]); break; // vnsin
|
|
DISABLE;
|
|
break;
|
|
case 28: // d[i] = 1.0f / expf(s[i] * (float)M_LOG2E); break; // vrexp2
|
|
DISABLE;
|
|
break;
|
|
}
|
|
}
|
|
|
|
fpr.MapRegsV(dregs, sz, MAP_NOINIT | MAP_DIRTY);
|
|
for (int i = 0; i < n; ++i)
|
|
{
|
|
VMOV(fpr.V(dregs[i]), tempxregs[i]);
|
|
}
|
|
|
|
ApplyPrefixD(dregs, sz);
|
|
|
|
fpr.ReleaseSpillLocks();
|
|
}
|
|
|
|
void Jit::Comp_Mftv(u32 op)
|
|
{
|
|
CONDITIONAL_DISABLE;
|
|
|
|
int imm = op & 0xFF;
|
|
int rt = _RT;
|
|
switch ((op >> 21) & 0x1f)
|
|
{
|
|
case 3: //mfv / mfvc
|
|
// rt = 0, imm = 255 appears to be used as a CPU interlock by some games.
|
|
if (rt != 0) {
|
|
if (imm < 128) { //R(rt) = VI(imm);
|
|
fpr.FlushV(imm);
|
|
gpr.MapReg(rt, MAP_NOINIT | MAP_DIRTY);
|
|
LDR(gpr.R(rt), CTXREG, fpr.GetMipsRegOffsetV(imm));
|
|
} else if (imm < 128 + VFPU_CTRL_MAX) { //mtvc
|
|
DISABLE;
|
|
// In case we have a saved prefix.
|
|
//FlushPrefixV();
|
|
//gpr.BindToRegister(rt, false, true);
|
|
//MOV(32, gpr.R(rt), M(¤tMIPS->vfpuCtrl[imm - 128]));
|
|
} else {
|
|
//ERROR - maybe need to make this value too an "interlock" value?
|
|
_dbg_assert_msg_(CPU,0,"mfv - invalid register");
|
|
}
|
|
}
|
|
break;
|
|
|
|
case 7: //mtv
|
|
if (imm < 128) {
|
|
gpr.FlushR(rt);
|
|
fpr.MapRegV(imm, MAP_DIRTY | MAP_NOINIT);
|
|
VLDR(fpr.V(imm), CTXREG, gpr.GetMipsRegOffset(rt));
|
|
} else if (imm < 128 + VFPU_CTRL_MAX) { //mtvc //currentMIPS->vfpuCtrl[imm - 128] = R(rt);
|
|
DISABLE;
|
|
//gpr.BindToRegister(rt, true, false);
|
|
//MOV(32, M(¤tMIPS->vfpuCtrl[imm - 128]), gpr.R(rt));
|
|
|
|
// TODO: Optimization if rt is Imm?
|
|
//if (imm - 128 == VFPU_CTRL_SPREFIX) {
|
|
//js.prefixSFlag = JitState::PREFIX_UNKNOWN;
|
|
//} else if (imm - 128 == VFPU_CTRL_TPREFIX) {
|
|
// js.prefixTFlag = JitState::PREFIX_UNKNOWN;
|
|
//} else if (imm - 128 == VFPU_CTRL_DPREFIX) {
|
|
// js.prefixDFlag = JitState::PREFIX_UNKNOWN;
|
|
//}
|
|
} else {
|
|
//ERROR
|
|
_dbg_assert_msg_(CPU,0,"mtv - invalid register");
|
|
}
|
|
break;
|
|
|
|
default:
|
|
DISABLE;
|
|
}
|
|
}
|
|
|
|
void Jit::Comp_Vmtvc(u32 op) {
|
|
DISABLE;
|
|
|
|
int vs = _VS;
|
|
int imm = op & 0xFF;
|
|
if (imm >= 128 && imm < 128 + VFPU_CTRL_MAX) {
|
|
fpr.MapRegV(vs, 0);
|
|
ADD(R0, CTXREG, offsetof(MIPSState, vfpuCtrl[0]) + (imm - 128) * 4);
|
|
VSTR(fpr.V(vs), R0, 0);
|
|
fpr.ReleaseSpillLocks();
|
|
|
|
if (imm - 128 == VFPU_CTRL_SPREFIX) {
|
|
js.prefixSFlag = ArmJitState::PREFIX_UNKNOWN;
|
|
} else if (imm - 128 == VFPU_CTRL_TPREFIX) {
|
|
js.prefixTFlag = ArmJitState::PREFIX_UNKNOWN;
|
|
} else if (imm - 128 == VFPU_CTRL_DPREFIX) {
|
|
js.prefixDFlag = ArmJitState::PREFIX_UNKNOWN;
|
|
}
|
|
}
|
|
}
|
|
|
|
void Jit::Comp_Vmmov(u32 op) {
|
|
DISABLE;
|
|
}
|
|
|
|
void Jit::Comp_VScl(u32 op) {
|
|
DISABLE;
|
|
}
|
|
|
|
void Jit::Comp_Vmmul(u32 op) {
|
|
DISABLE;
|
|
}
|
|
|
|
void Jit::Comp_Vmscl(u32 op) {
|
|
DISABLE;
|
|
}
|
|
|
|
void Jit::Comp_Vtfm(u32 op) {
|
|
DISABLE;
|
|
}
|
|
|
|
void Jit::Comp_VHdp(u32 op) {
|
|
DISABLE;
|
|
}
|
|
|
|
void Jit::Comp_VCrs(u32 op) {
|
|
DISABLE;
|
|
}
|
|
|
|
void Jit::Comp_VDet(u32 op) {
|
|
DISABLE;
|
|
}
|
|
|
|
void Jit::Comp_Vi2x(u32 op) {
|
|
DISABLE;
|
|
}
|
|
|
|
void Jit::Comp_Vx2i(u32 op) {
|
|
DISABLE;
|
|
}
|
|
|
|
void Jit::Comp_Vf2i(u32 op) {
|
|
DISABLE;
|
|
}
|
|
|
|
void Jit::Comp_Vi2f(u32 op) {
|
|
DISABLE;
|
|
}
|
|
|
|
void Jit::Comp_Vcst(u32 op) {
|
|
DISABLE;
|
|
}
|
|
|
|
void Jit::Comp_Vhoriz(u32 op) {
|
|
DISABLE;
|
|
}
|
|
|
|
}
|