mirror of
https://github.com/hrydgard/ppsspp.git
synced 2025-04-02 11:01:50 -04:00
41f5abab31
Now builds on Playbook and Dev Alpha Make emulator more compatible with other OS (case sensitivity, defines, includes) Uses Android's code paths and backend
356 lines
8.3 KiB
C++
356 lines
8.3 KiB
C++
// Copyright (c) 2012- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include "../../HLE/HLE.h"
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#include "../MIPS.h"
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#include "../MIPSCodeUtils.h"
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#include "../MIPSAnalyst.h"
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#include "../MIPSTables.h"
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#include "Jit.h"
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#include "RegCache.h"
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#include "JitCache.h"
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#include <ArmEmitter.h>
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#define _RS ((op>>21) & 0x1F)
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#define _RT ((op>>16) & 0x1F)
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#define _RD ((op>>11) & 0x1F)
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#define _FS ((op>>11) & 0x1F)
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#define _FT ((op>>16) & 0x1F)
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#define _FD ((op>>6 ) & 0x1F)
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#define _POS ((op>>6 ) & 0x1F)
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#define _SIZE ((op>>11 ) & 0x1F)
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#define LOOPOPTIMIZATION 0
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using namespace MIPSAnalyst;
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namespace MIPSComp
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{
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/*
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void Jit::BranchRSRTComp(u32 op, Gen::CCFlags cc, bool likely)
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{
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int offset = (signed short)(op&0xFFFF)<<2;
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int rt = _RT;
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int rs = _RS;
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u32 targetAddr = js.compilerPC + offset + 4;
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u32 delaySlotOp = Memory::ReadUnchecked_U32(js.compilerPC+4);
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//Compile the delay slot
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bool delaySlotIsNice = GetOutReg(delaySlotOp) != rt && GetOutReg(delaySlotOp) != rs;// IsDelaySlotNice(op, delaySlotOp);
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if (!delaySlotIsNice)
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{
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ERROR_LOG(CPU, "Not nice delay slot in BranchRSRTComp :( %08x", js.compilerPC);
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}
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// The delay slot being nice doesn't really matter though...
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if (rs == 0)
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{
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CMP(32, gpr.R(rt), Imm32(0));
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}
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else
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{
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gpr.BindToRegister(rs, true, false);
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CMP(32, gpr.R(rs), rt == 0 ? Imm32(0) : gpr.R(rt));
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}
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FlushAll();
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js.inDelaySlot = true;
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Gen::FixupBranch ptr;
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if (!likely)
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{
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PUSHF(); // preserve flag around the delay slot!
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CompileAt(js.compilerPC + 4);
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FlushAll();
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POPF(); // restore flag!
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ptr = J_CC(cc, true);
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}
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else
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{
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ptr = J_CC(cc, true);
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CompileAt(js.compilerPC + 4);
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FlushAll();
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}
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js.inDelaySlot = false;
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// Take the branch
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WriteExit(targetAddr, 0);
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SetJumpTarget(ptr);
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// Not taken
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WriteExit(js.compilerPC+8, 1);
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js.compiling = false;
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}
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*/
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/*
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void Jit::BranchRSZeroComp(u32 op, Gen::CCFlags cc, bool likely)
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{
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int offset = (signed short)(op&0xFFFF)<<2;
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int rs = _RS;
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u32 targetAddr = js.compilerPC + offset + 4;
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u32 delaySlotOp = Memory::ReadUnchecked_U32(js.compilerPC + 4);
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bool delaySlotIsNice = GetOutReg(delaySlotOp) != rs;
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if (!delaySlotIsNice)
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{
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ERROR_LOG(CPU, "Not nice delay slot in BranchRSZeroComp :( %08x", js.compilerPC);
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}
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gpr.BindToRegister(rs, true, false);
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CMP(32, gpr.R(rs), Imm32(0));
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FlushAll();
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Gen::FixupBranch ptr;
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js.inDelaySlot = true;
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if (!likely)
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{
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PUSHF(); // preserve flag around the delay slot! Better hope the delay slot instruction doesn't need to fall back to interpreter...
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CompileAt(js.compilerPC + 4);
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FlushAll();
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POPF(); // restore flag!
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ptr = J_CC(cc, true);
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}
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else
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{
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ptr = J_CC(cc, true);
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CompileAt(js.compilerPC + 4);
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FlushAll();
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}
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js.inDelaySlot = false;
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// Take the branch
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WriteExit(targetAddr, 0);
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SetJumpTarget(ptr);
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// Not taken
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WriteExit(js.compilerPC + 8, 1);
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js.compiling = false;
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}
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*/
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void Jit::Comp_RelBranch(u32 op)
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{
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/*
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switch (op>>26)
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{
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case 4: BranchRSRTComp(op, CC_NZ, false); break;//beq
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case 5: BranchRSRTComp(op, CC_Z, false); break;//bne
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case 6: BranchRSZeroComp(op, CC_G, false); break;//blez
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case 7: BranchRSZeroComp(op, CC_LE, false); break;//bgtz
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case 20: BranchRSRTComp(op, CC_NZ, true); break;//beql
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case 21: BranchRSRTComp(op, CC_Z, true); break;//bnel
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case 22: BranchRSZeroComp(op, CC_G, true); break;//blezl
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case 23: BranchRSZeroComp(op, CC_LE, true); break;//bgtzl
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default:
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_dbg_assert_msg_(CPU,0,"Trying to compile instruction that can't be compiled");
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break;
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}
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*/
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js.compiling = false;
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}
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void Jit::Comp_RelBranchRI(u32 op)
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{
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/*
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switch ((op >> 16) & 0x1F)
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{
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case 0: BranchRSZeroComp(op, CC_GE, false); break; //if ((s32)R(rs) < 0) DelayBranchTo(addr); else PC += 4; break;//bltz
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case 1: BranchRSZeroComp(op, CC_L, false); break; //if ((s32)R(rs) >= 0) DelayBranchTo(addr); else PC += 4; break;//bgez
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case 2: BranchRSZeroComp(op, CC_GE, true); break; //if ((s32)R(rs) < 0) DelayBranchTo(addr); else PC += 8; break;//bltzl
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case 3: BranchRSZeroComp(op, CC_L, true); break; //if ((s32)R(rs) >= 0) DelayBranchTo(addr); else PC += 8; break;//bgezl
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default:
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_dbg_assert_msg_(CPU,0,"Trying to compile instruction that can't be compiled");
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break;
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}
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*/
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js.compiling = false;
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}
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// If likely is set, discard the branch slot if NOT taken.
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/*
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void Jit::BranchFPFlag(u32 op, Gen::CCFlags cc, bool likely)
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{
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int offset = (signed short)(op & 0xFFFF) << 2;
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u32 targetAddr = js.compilerPC + offset + 4;
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u32 delaySlotOp = Memory::ReadUnchecked_U32(js.compilerPC + 4);
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bool delaySlotIsNice = IsDelaySlotNice(op, delaySlotOp);
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if (!delaySlotIsNice)
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{
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ERROR_LOG(CPU, "Not nice delay slot in BranchFPFlag :(");
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}
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FlushAll();
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TEST(32, M((void *)&(mips_->fpcond)), Imm32(1));
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Gen::FixupBranch ptr;
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js.inDelaySlot = true;
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if (!likely)
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{
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PUSHF(); // preserve flag around the delay slot!
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CompileAt(js.compilerPC + 4);
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FlushAll();
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POPF(); // restore flag!
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ptr = J_CC(cc, true);
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}
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else
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{
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ptr = J_CC(cc, true);
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CompileAt(js.compilerPC + 4);
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FlushAll();
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}
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js.inDelaySlot = false;
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// Take the branch
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WriteExit(targetAddr, 0);
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SetJumpTarget(ptr);
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// Not taken
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WriteExit(js.compilerPC + 8, 1);
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js.compiling = false;
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}
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*/
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void Jit::Comp_FPUBranch(u32 op)
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{
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/*
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switch((op >> 16) & 0x1f)
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{
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case 0: BranchFPFlag(op, CC_NZ, false); break; // bc1f
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case 1: BranchFPFlag(op, CC_Z, false); break; // bc1t
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case 2: BranchFPFlag(op, CC_NZ, true); break; // bc1fl
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case 3: BranchFPFlag(op, CC_Z, true); break; // bc1tl
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default:
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_dbg_assert_msg_(CPU,0,"Trying to interpret instruction that can't be interpreted");
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break;
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}
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*/
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js.compiling = false;
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}
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void Jit::Comp_VBranch(u32 op)
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{
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/*
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Comp_Generic(op + 4);
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Comp_Generic(op);
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js.compiling = false;
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return;
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int imm = (signed short)(op&0xFFFF)<<2;
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u32 targetAddr = js.compilerPC + imm + 4;
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int imm3 = (op >> 18) & 7;
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int val = (mips_->vfpuCtrl[VFPU_CTRL_CC] >> imm3) & 1;
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switch ((op >> 16) & 3)
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{
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//case 0: if (!val) DelayBranchTo(addr); else PC += 4; break; //bvf
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//case 1: if ( val) DelayBranchTo(addr); else PC += 4; break; //bvt
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//case 2: if (!val) DelayBranchTo(addr); else PC += 8; break; //bvfl
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//case 3: if ( val) DelayBranchTo(addr); else PC += 8; break; //bvtl
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//TODO
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}
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js.compiling = false;
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*/
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}
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void Jit::Comp_Jump(u32 op)
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{
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/*
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u32 off = ((op & 0x3FFFFFF) << 2);
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u32 targetAddr = (js.compilerPC & 0xF0000000) | off;
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//Delay slot
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CompileAt(js.compilerPC + 4);
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FlushAll();
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switch (op >> 26)
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{
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case 2: //j
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WriteExit(targetAddr, 0);
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break;
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case 3: //jal
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MOV(32, M(&mips_->r[MIPS_REG_RA]), Imm32(js.compilerPC + 8)); // Save return address
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WriteExit(targetAddr, 0);
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break;
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default:
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_dbg_assert_msg_(CPU,0,"Trying to compile instruction that can't be compiled");
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break;
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}
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js.compiling = false;
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*/
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}
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void Jit::Comp_JumpReg(u32 op)
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{
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/*
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int rs = _RS;
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u32 delaySlotOp = Memory::ReadUnchecked_U32(js.compilerPC + 4);
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bool delaySlotIsNice = GetOutReg(delaySlotOp) != rs;
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// Do what with that information?
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gpr.BindToRegister(rs, true, false);
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PUSH(32, gpr.R(rs));
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CompileAt(js.compilerPC + 4);
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FlushAll();
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POP(32, R(EAX));
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switch (op & 0x3f)
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{
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case 8: //jr
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break;
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case 9: //jalr
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MOV(32, M(&mips_->r[MIPS_REG_RA]), Imm32(js.compilerPC + 8));
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break;
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default:
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_dbg_assert_msg_(CPU,0,"Trying to compile instruction that can't be compiled");
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break;
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}
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WriteExitDestInEAX();
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js.compiling = false;
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*/
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}
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void Jit::Comp_Syscall(u32 op)
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{
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/*
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FlushAll();
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MOV(32, R(EAX), M(&mips_->r[MIPS_REG_RA]));
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MOV(32, M(&mips_->pc), R(EAX));
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ABI_CallFunctionC(&CallSyscall, op);
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WriteSyscallExit();*/
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}
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} // namespace Mipscomp
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