mirror of
https://github.com/hrydgard/ppsspp.git
synced 2025-04-02 11:01:50 -04:00
41f5abab31
Now builds on Playbook and Dev Alpha Make emulator more compatible with other OS (case sensitivity, defines, includes) Uses Android's code paths and backend
306 lines
7.3 KiB
C++
306 lines
7.3 KiB
C++
// Copyright (c) 2012- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include "Jit.h"
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#include "RegCache.h"
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#include <ArmEmitter.h>
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using namespace MIPSAnalyst;
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#define _RS ((op>>21) & 0x1F)
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#define _RT ((op>>16) & 0x1F)
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#define _RD ((op>>11) & 0x1F)
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#define _FS ((op>>11) & 0x1F)
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#define _FT ((op>>16) & 0x1F)
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#define _FD ((op>>6 ) & 0x1F)
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#define _SA ((op>>6 ) & 0x1F)
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#define _POS ((op>>6 ) & 0x1F)
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#define _SIZE ((op>>11 ) & 0x1F)
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#define OLDD Comp_Generic(op); return;
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namespace MIPSComp
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{
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/*
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void Jit::CompImmLogic(u32 op, void (XEmitter::*arith)(int, const OpArg &, const OpArg &))
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{
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u32 uimm = (u16)(op & 0xFFFF);
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int rt = _RT;
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int rs = _RS;
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gpr.Lock(rt, rs);
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gpr.BindToRegister(rt, rt == rs, true);
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if (rt != rs)
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MOV(32, gpr.R(rt), gpr.R(rs));
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(this->*arith)(32, gpr.R(rt), Imm32(uimm));
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gpr.UnlockAll();
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}
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*/
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void Jit::Comp_IType(u32 op)
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{
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OLDD
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/*
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s32 simm = (s16)(op & 0xFFFF);
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u32 uimm = (u16)(op & 0xFFFF);
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int rt = _RT;
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int rs = _RS;
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switch (op >> 26)
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{
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case 8: // same as addiu?
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case 9: //R(rt) = R(rs) + simm; break; //addiu
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{
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if (gpr.R(rs).IsImm())
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{
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gpr.SetImmediate32(rt, gpr.R(rs).GetImmValue() + simm);
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break;
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}
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gpr.Lock(rt, rs);
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if (rs != 0)
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{
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gpr.BindToRegister(rt, rt == rs, true);
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if (rt != rs)
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MOV(32, gpr.R(rt), gpr.R(rs));
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if (simm != 0)
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ADD(32, gpr.R(rt), Imm32((u32)(s32)simm));
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// TODO: Can also do LEA if both operands happen to be in registers.
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}
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else
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{
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gpr.SetImmediate32(rt, simm);
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}
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gpr.UnlockAll();
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}
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break;
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case 10: // R(rt) = (s32)R(rs) < simm; break; //slti
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gpr.Lock(rt, rs);
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gpr.BindToRegister(rt, rt == rs, true);
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XOR(32, R(EAX), R(EAX));
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CMP(32, gpr.R(rs), Imm32(simm));
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SETcc(CC_L, R(EAX));
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MOV(32, gpr.R(rt), R(EAX));
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gpr.UnlockAll();
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break;
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case 11: // R(rt) = R(rs) < uimm; break; //sltiu
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gpr.Lock(rt, rs);
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gpr.BindToRegister(rt, rt == rs, true);
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XOR(32, R(EAX), R(EAX));
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CMP(32, gpr.R(rs), Imm32((u32)simm));
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SETcc(CC_B, R(EAX));
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MOV(32, gpr.R(rt), R(EAX));
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gpr.UnlockAll();
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break;
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case 12: CompImmLogic(op, &XEmitter::AND); break;
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case 13: CompImmLogic(op, &XEmitter::OR); break;
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case 14: CompImmLogic(op, &XEmitter::XOR); break;
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case 15: //R(rt) = uimm << 16; break; //lui
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gpr.SetImmediate32(rt, uimm << 16);
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break;
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default:
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Comp_Generic(op);
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break;
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}*/
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}
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//rd = rs X rt
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/*
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void Jit::CompTriArith(u32 op, void (XEmitter::*arith)(int, const OpArg &, const OpArg &))
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{
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int rt = _RT;
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int rs = _RS;
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int rd = _RD;
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gpr.Lock(rt, rs, rd);
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MOV(32, R(EAX), gpr.R(rs));
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MOV(32, R(EBX), gpr.R(rt));
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gpr.BindToRegister(rd, true, true);
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(this->*arith)(32, R(EAX), R(EBX));
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MOV(32, gpr.R(rd), R(EAX));
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gpr.UnlockAll();
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}
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*/
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void Jit::Comp_RType3(u32 op)
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{
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OLDD
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int rt = _RT;
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int rs = _RS;
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int rd = _RD;
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gpr.Lock(rd, rs, rt);
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gpr.BindToRegister(rs, true, false);
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gpr.BindToRegister(rt, true, false);
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gpr.BindToRegister(rd, true, true);
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switch (op & 63)
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{
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//case 10: if (!R(rt)) R(rd) = R(rs); break; //movz
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//case 11: if (R(rt)) R(rd) = R(rs); break; //movn
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// case 32: //R(rd) = R(rs) + R(rt); break; //add
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case 33: //R(rd) = R(rs) + R(rt); break; //addu
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ADD(gpr.RX(rd), gpr.RX(rs), gpr.RX(rt));
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break;
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case 134: //R(rd) = R(rs) - R(rt); break; //sub
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case 135:
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SUB(gpr.RX(rd), gpr.RX(rs), gpr.RX(rt));
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break;
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case 136: //R(rd) = R(rs) & R(rt); break; //and
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AND(gpr.RX(rd), gpr.RX(rs), gpr.RX(rt));
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break;
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case 137: //R(rd) = R(rs) | R(rt); break; //or
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ORR(gpr.RX(rd), gpr.RX(rs), gpr.RX(rt));
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break;
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case 138: //R(rd) = R(rs) ^ R(rt); break; //xor/eor
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EOR(gpr.RX(rd), gpr.RX(rs), gpr.RX(rt));
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break;
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case 39: // R(rd) = ~(R(rs) | R(rt)); //nor
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ORR(gpr.RX(rd), gpr.RX(rs), gpr.RX(rt));
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MVN(gpr.RX(rd), gpr.RX(rd));
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break;
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case 42: //R(rd) = (int)R(rs) < (int)R(rt); break; //slt
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CMP(gpr.RX(rs), gpr.RX(rt));
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SetCC(CC_LT);
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ARMABI_MOVI2R(gpr.RX(rd), 1);
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SetCC(CC_GE);
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ARMABI_MOVI2R(gpr.RX(rd), 0);
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SetCC(CC_AL);
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break;
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case 43: //R(rd) = R(rs) < R(rt); break; //sltu
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CMP(gpr.RX(rs), gpr.RX(rt));
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SetCC(CC_LO);
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ARMABI_MOVI2R(gpr.RX(rd), 1);
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SetCC(CC_HS);
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ARMABI_MOVI2R(gpr.RX(rd), 0);
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SetCC(CC_AL);
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break;
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// case 44: R(rd) = (R(rs) > R(rt)) ? R(rs) : R(rt); break; //max
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// CMP(a,b); CMOVLT(a,b)
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// case 45: R(rd) = (R(rs) < R(rt)) ? R(rs) : R(rt); break; //min
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// CMP(a,b); CMOVGT(a,b)
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default:
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gpr.UnlockAll();
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Comp_Generic(op);
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break;
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}
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gpr.UnlockAll();
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}
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/*
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void Jit::CompShiftImm(u32 op, void (XEmitter::*shift)(int, OpArg, OpArg))
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{
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int rd = _RD;
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int rt = _RT;
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gpr.Lock(rd, rt);
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int sa = _SA;
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gpr.BindToRegister(rd, rd == rt, true);
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if (rd != rt)
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MOV(32, gpr.R(rd), gpr.R(rt));
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(this->*shift)(32, gpr.R(rd), Imm8(sa));
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gpr.UnlockAll();
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}
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*/
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// "over-shifts" work the same as on x86 - only bottom 5 bits are used to get the shift value
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/*
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void Jit::CompShiftVar(u32 op, void (XEmitter::*shift)(int, OpArg, OpArg))
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{
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int rd = _RD;
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int rt = _RT;
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int rs = _RS;
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gpr.FlushLockX(ECX);
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gpr.Lock(rd, rt, rs);
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gpr.BindToRegister(rd, true, true);
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if (rd != rt)
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MOV(32, gpr.R(rd), gpr.R(rt));
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MOV(32, R(ECX), gpr.R(rs)); // Only ECX can be used for variable shifts.
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AND(32, R(ECX), Imm32(0x1f));
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(this->*shift)(32, gpr.R(rd), R(ECX));
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gpr.UnlockAll();
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gpr.UnlockAllX();
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}
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*/
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void Jit::Comp_ShiftType(u32 op)
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{
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// WARNIGN : ROTR
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OLDD
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switch (op & 0x3f)
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{
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//case 0: CompShiftImm(op, &ARMXEmitter::SHL); break;
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//case 2: CompShiftImm(op, &XEmitter::SHR); break; // srl
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//case 3: CompShiftImm(op, &XEmitter::SAR); break; // sra
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// case 4: CompShiftVar(op, &XEmitter::SHL); break; // R(rd) = R(rt) << R(rs); break; //sllv
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// case 6: CompShiftVar(op, &XEmitter::SHR); break; // R(rd) = R(rt) >> R(rs); break; //srlv
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// case 7: CompShiftVar(op, &XEmitter::SAR); break; // R(rd) = ((s32)R(rt)) >> R(rs); break; //srav
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default:
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Comp_Generic(op);
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//_dbg_assert_msg_(CPU,0,"Trying to interpret instruction that can't be interpreted");
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break;
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}
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}
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void Jit::Comp_Allegrex(u32 op)
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{
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OLDD
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int rt = _RT;
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int rd = _RD;
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switch ((op >> 6) & 31)
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{
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case 16: // seb // R(rd) = (u32)(s32)(s8)(u8)R(rt);
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/*
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gpr.Lock(rd, rt);
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gpr.BindToRegister(rd, true, true);
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MOV(32, R(EAX), gpr.R(rt)); // work around the byte-register addressing problem
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MOVSX(32, 8, gpr.RX(rd), R(EAX));
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gpr.UnlockAll();*/
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break;
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case 24: // seh
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/*
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gpr.Lock(rd, rt);
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gpr.BindToRegister(rd, true, true);
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MOVSX(32, 16, gpr.RX(rd), gpr.R(rt));
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gpr.UnlockAll();*/
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break;
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case 20: //bitrev
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default:
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Comp_Generic(op);
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return;
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}
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}
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}
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