mirror of
https://github.com/hrydgard/ppsspp.git
synced 2025-04-02 11:01:50 -04:00
1cb7965cb1
When these are invalidated, the block they point to gets invalidated too. Will be useful to implement various types of block merging and function inlining without affecting correctness of cache clears etc. Also, with this commit we can now fully inline replaced functions. fabsf() boils down to 1-2 instructions and the block continues, for example.
700 lines
20 KiB
C++
700 lines
20 KiB
C++
// Copyright (c) 2012- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include "Core/Reporting.h"
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#include "Core/Config.h"
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#include "Core/HLE/HLE.h"
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#include "Core/HLE/HLETables.h"
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#include "Core/Host.h"
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#include "Core/MIPS/MIPS.h"
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#include "Core/MIPS/MIPSCodeUtils.h"
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#include "Core/MIPS/MIPSAnalyst.h"
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#include "Core/MIPS/MIPSTables.h"
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#include "Core/MIPS/x86/Jit.h"
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#include "Core/MIPS/x86/RegCache.h"
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#include "Core/MIPS/JitCommon/JitBlockCache.h"
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#define _RS MIPS_GET_RS(op)
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#define _RT MIPS_GET_RT(op)
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#define _RD MIPS_GET_RD(op)
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#define _FS MIPS_GET_FS(op)
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#define _FT MIPS_GET_FT(op)
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#define _FD MIPS_GET_FD(op)
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#define _SA MIPS_GET_SA(op)
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#define _POS ((op>> 6) & 0x1F)
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#define _SIZE ((op>>11) & 0x1F)
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#define _IMM16 (signed short)(op & 0xFFFF)
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#define _IMM26 (op & 0x03FFFFFF)
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#define LOOPOPTIMIZATION 0
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using namespace MIPSAnalyst;
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// NOTE: Can't use CONDITIONAL_DISABLE in this file, branches are so special
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// that they cannot be interpreted in the context of the Jit.
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// But we can at least log and compare.
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// #define DO_CONDITIONAL_LOG 1
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#define DO_CONDITIONAL_LOG 0
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// We can also disable nice delay slots.
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// #define CONDITIONAL_NICE_DELAYSLOT delaySlotIsNice = false;
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#define CONDITIONAL_NICE_DELAYSLOT ;
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#if DO_CONDITIONAL_LOG
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#define CONDITIONAL_LOG BranchLog(op);
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#define CONDITIONAL_LOG_EXIT(addr) BranchLogExit(op, addr, false);
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#define CONDITIONAL_LOG_EXIT_EAX() BranchLogExit(op, 0, true);
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#else
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#define CONDITIONAL_LOG ;
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#define CONDITIONAL_LOG_EXIT(addr) ;
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#define CONDITIONAL_LOG_EXIT_EAX() ;
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#endif
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namespace MIPSComp
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{
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static u32 intBranchExit;
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static u32 jitBranchExit;
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static void JitBranchLog(MIPSOpcode op, u32 pc)
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{
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currentMIPS->pc = pc;
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currentMIPS->inDelaySlot = false;
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MIPSInterpretFunc func = MIPSGetInterpretFunc(op);
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MIPSInfo info = MIPSGetInfo(op);
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func(op);
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// Branch taken, use nextPC.
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if (currentMIPS->inDelaySlot)
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intBranchExit = currentMIPS->nextPC;
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else
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{
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// Branch not taken, likely delay slot skipped.
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if (info & LIKELY)
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intBranchExit = currentMIPS->pc;
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// Branch not taken, so increment over delay slot.
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else
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intBranchExit = currentMIPS->pc + 4;
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}
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currentMIPS->pc = pc;
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currentMIPS->inDelaySlot = false;
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}
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static void JitBranchLogMismatch(MIPSOpcode op, u32 pc)
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{
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char temp[256];
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MIPSDisAsm(op, pc, temp, true);
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ERROR_LOG(JIT, "Bad jump: %s - int:%08x jit:%08x", temp, intBranchExit, jitBranchExit);
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host->SetDebugMode(true);
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}
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void Jit::BranchLog(MIPSOpcode op)
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{
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FlushAll();
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ABI_CallFunctionCC(thunks.ProtectFunction((void *) &JitBranchLog, 2), op.encoding, js.compilerPC);
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}
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void Jit::BranchLogExit(MIPSOpcode op, u32 dest, bool useEAX)
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{
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OpArg destArg = useEAX ? R(EAX) : Imm32(dest);
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CMP(32, M((void *) &intBranchExit), destArg);
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FixupBranch skip = J_CC(CC_E);
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MOV(32, M((void *) &jitBranchExit), destArg);
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ABI_CallFunctionCC(thunks.ProtectFunction((void *) &JitBranchLogMismatch, 2), op.encoding, js.compilerPC);
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// Restore EAX, we probably ruined it.
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if (useEAX)
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MOV(32, R(EAX), M((void *) &jitBranchExit));
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SetJumpTarget(skip);
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}
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static CCFlags FlipCCFlag(CCFlags flag)
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{
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switch (flag)
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{
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case CC_O: return CC_NO;
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case CC_NO: return CC_O;
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case CC_B: return CC_NB;
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case CC_NB: return CC_B;
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case CC_Z: return CC_NZ;
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case CC_NZ: return CC_Z;
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case CC_BE: return CC_NBE;
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case CC_NBE: return CC_BE;
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case CC_S: return CC_NS;
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case CC_NS: return CC_S;
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case CC_P: return CC_NP;
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case CC_NP: return CC_P;
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case CC_L: return CC_NL;
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case CC_NL: return CC_L;
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case CC_LE: return CC_NLE;
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case CC_NLE: return CC_LE;
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}
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ERROR_LOG_REPORT(JIT, "FlipCCFlag: Unexpected CC flag: %d", flag);
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return CC_O;
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}
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bool Jit::PredictTakeBranch(u32 targetAddr, bool likely) {
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// If it's likely, it's... probably likely, right?
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if (likely)
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return true;
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// TODO: Normal branch prediction would be to take branches going upward to lower addresses.
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// However, this results in worse performance as of this comment's writing.
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// The reverse check generally gives better or same performance.
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return targetAddr > js.compilerPC;
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}
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void Jit::CompBranchExits(CCFlags cc, u32 targetAddr, u32 notTakenAddr, bool delaySlotIsNice, bool likely, bool andLink) {
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// We may want to try to continue along this branch a little while, to reduce reg flushing.
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if (CanContinueBranch())
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{
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bool predictTakeBranch = PredictTakeBranch(targetAddr, likely);
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if (predictTakeBranch)
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cc = FlipCCFlag(cc);
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Gen::FixupBranch ptr;
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RegCacheState state;
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if (!likely)
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{
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if (!delaySlotIsNice)
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CompileDelaySlot(DELAYSLOT_SAFE);
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ptr = J_CC(cc, true);
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GetStateAndFlushAll(state);
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}
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else
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{
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ptr = J_CC(cc, true);
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if (predictTakeBranch)
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GetStateAndFlushAll(state);
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else
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CompileDelaySlot(DELAYSLOT_FLUSH);
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}
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if (predictTakeBranch)
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{
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// We flipped the cc, the not taken case is first.
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CONDITIONAL_LOG_EXIT(notTakenAddr);
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WriteExit(notTakenAddr, js.nextExit++);
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// Now our taken path. Bring the regs back, we didn't flush 'em after all.
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SetJumpTarget(ptr);
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RestoreState(state);
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CONDITIONAL_LOG_EXIT(targetAddr);
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if (andLink)
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gpr.SetImm(MIPS_REG_RA, js.compilerPC + 8);
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// Don't forget to run the delay slot if likely.
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if (likely)
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CompileDelaySlot(DELAYSLOT_NICE);
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// Account for the increment in the loop.
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js.compilerPC = targetAddr - 4;
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// In case the delay slot was a break or something.
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js.compiling = true;
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}
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else
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{
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// Take the branch
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if (andLink)
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MOV(32, M(&mips_->r[MIPS_REG_RA]), Imm32(js.compilerPC + 8));
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CONDITIONAL_LOG_EXIT(targetAddr);
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WriteExit(targetAddr, js.nextExit++);
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// Not taken
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SetJumpTarget(ptr);
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RestoreState(state);
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CONDITIONAL_LOG_EXIT(notTakenAddr);
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// Account for the delay slot.
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js.compilerPC += 4;
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// In case the delay slot was a break or something.
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js.compiling = true;
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}
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}
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else
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{
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Gen::FixupBranch ptr;
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if (!likely)
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{
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if (!delaySlotIsNice)
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CompileDelaySlot(DELAYSLOT_SAFE_FLUSH);
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else
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FlushAll();
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ptr = J_CC(cc, true);
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}
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else
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{
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FlushAll();
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ptr = J_CC(cc, true);
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CompileDelaySlot(DELAYSLOT_FLUSH);
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}
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// Take the branch
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if (andLink)
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MOV(32, M(&mips_->r[MIPS_REG_RA]), Imm32(js.compilerPC + 8));
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CONDITIONAL_LOG_EXIT(targetAddr);
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WriteExit(targetAddr, js.nextExit++);
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// Not taken
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SetJumpTarget(ptr);
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CONDITIONAL_LOG_EXIT(notTakenAddr);
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WriteExit(notTakenAddr, js.nextExit++);
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js.compiling = false;
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}
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}
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void Jit::BranchRSRTComp(MIPSOpcode op, Gen::CCFlags cc, bool likely)
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{
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CONDITIONAL_LOG;
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if (js.inDelaySlot) {
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ERROR_LOG_REPORT(JIT, "Branch in RSRTComp delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
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return;
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}
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int offset = _IMM16 << 2;
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MIPSGPReg rt = _RT;
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MIPSGPReg rs = _RS;
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u32 targetAddr = js.compilerPC + offset + 4;
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if (jo.immBranches && gpr.IsImm(rs) && gpr.IsImm(rt) && js.numInstructions < jo.continueMaxInstructions)
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{
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// The cc flags are opposites: when NOT to take the branch.
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bool skipBranch;
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s32 rsImm = (s32)gpr.GetImm(rs);
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s32 rtImm = (s32)gpr.GetImm(rt);
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switch (cc)
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{
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case CC_E: skipBranch = rsImm == rtImm; break;
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case CC_NE: skipBranch = rsImm != rtImm; break;
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default: skipBranch = false; _dbg_assert_msg_(JIT, false, "Bad cc flag in BranchRSRTComp().");
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}
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if (skipBranch)
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{
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// Skip the delay slot if likely, otherwise it'll be the next instruction.
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if (likely)
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js.compilerPC += 4;
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return;
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}
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// Branch taken. Always compile the delay slot, and then go to dest.
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CompileDelaySlot(DELAYSLOT_NICE);
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// Account for the increment in the loop.
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js.compilerPC = targetAddr - 4;
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// In case the delay slot was a break or something.
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js.compiling = true;
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return;
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}
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MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC+4);
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bool delaySlotIsNice = IsDelaySlotNiceReg(op, delaySlotOp, rt, rs);
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CONDITIONAL_NICE_DELAYSLOT;
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if (!likely && delaySlotIsNice)
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CompileDelaySlot(DELAYSLOT_NICE);
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if (gpr.IsImm(rt) && gpr.GetImm(rt) == 0)
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{
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gpr.KillImmediate(rs, true, false);
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CMP(32, gpr.R(rs), Imm32(0));
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}
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else
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{
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gpr.MapReg(rs, true, false);
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CMP(32, gpr.R(rs), gpr.R(rt));
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}
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CompBranchExits(cc, targetAddr, js.compilerPC + 8, delaySlotIsNice, likely, false);
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}
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void Jit::BranchRSZeroComp(MIPSOpcode op, Gen::CCFlags cc, bool andLink, bool likely)
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{
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CONDITIONAL_LOG;
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if (js.inDelaySlot) {
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ERROR_LOG_REPORT(JIT, "Branch in RSZeroComp delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
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return;
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}
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int offset = _IMM16 << 2;
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MIPSGPReg rs = _RS;
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u32 targetAddr = js.compilerPC + offset + 4;
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if (jo.immBranches && gpr.IsImm(rs) && js.numInstructions < jo.continueMaxInstructions)
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{
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// The cc flags are opposites: when NOT to take the branch.
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bool skipBranch;
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s32 imm = (s32)gpr.GetImm(rs);
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switch (cc)
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{
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case CC_G: skipBranch = imm > 0; break;
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case CC_GE: skipBranch = imm >= 0; break;
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case CC_L: skipBranch = imm < 0; break;
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case CC_LE: skipBranch = imm <= 0; break;
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default: skipBranch = false; _dbg_assert_msg_(JIT, false, "Bad cc flag in BranchRSZeroComp().");
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}
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if (skipBranch)
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{
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// Skip the delay slot if likely, otherwise it'll be the next instruction.
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if (likely)
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js.compilerPC += 4;
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return;
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}
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// Branch taken. Always compile the delay slot, and then go to dest.
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CompileDelaySlot(DELAYSLOT_NICE);
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if (andLink)
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gpr.SetImm(MIPS_REG_RA, js.compilerPC + 8);
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// Account for the increment in the loop.
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js.compilerPC = targetAddr - 4;
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// In case the delay slot was a break or something.
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js.compiling = true;
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return;
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}
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MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4);
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bool delaySlotIsNice = IsDelaySlotNiceReg(op, delaySlotOp, rs);
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CONDITIONAL_NICE_DELAYSLOT;
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if (!likely && delaySlotIsNice)
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CompileDelaySlot(DELAYSLOT_NICE);
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gpr.MapReg(rs, true, false);
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CMP(32, gpr.R(rs), Imm32(0));
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CompBranchExits(cc, targetAddr, js.compilerPC + 8, delaySlotIsNice, likely, andLink);
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}
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void Jit::Comp_RelBranch(MIPSOpcode op)
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{
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switch (op>>26)
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{
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case 4: BranchRSRTComp(op, CC_NZ, false); break;//beq
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case 5: BranchRSRTComp(op, CC_Z, false); break;//bne
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case 6: BranchRSZeroComp(op, CC_G, false, false); break;//blez
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case 7: BranchRSZeroComp(op, CC_LE, false, false); break;//bgtz
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case 20: BranchRSRTComp(op, CC_NZ, true); break;//beql
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case 21: BranchRSRTComp(op, CC_Z, true); break;//bnel
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case 22: BranchRSZeroComp(op, CC_G, false, true); break;//blezl
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case 23: BranchRSZeroComp(op, CC_LE, false, true); break;//bgtzl
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default:
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_dbg_assert_msg_(CPU,0,"Trying to compile instruction that can't be compiled");
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break;
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}
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}
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void Jit::Comp_RelBranchRI(MIPSOpcode op)
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{
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switch ((op >> 16) & 0x1F)
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{
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case 0: BranchRSZeroComp(op, CC_GE, false, false); break; //if ((s32)R(rs) < 0) DelayBranchTo(addr); else PC += 4; break;//bltz
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case 1: BranchRSZeroComp(op, CC_L, false, false); break; //if ((s32)R(rs) >= 0) DelayBranchTo(addr); else PC += 4; break;//bgez
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case 2: BranchRSZeroComp(op, CC_GE, false, true); break; //if ((s32)R(rs) < 0) DelayBranchTo(addr); else PC += 8; break;//bltzl
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case 3: BranchRSZeroComp(op, CC_L, false, true); break; //if ((s32)R(rs) >= 0) DelayBranchTo(addr); else PC += 8; break;//bgezl
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case 16: BranchRSZeroComp(op, CC_GE, true, false); break; //R(MIPS_REG_RA) = PC + 8; if ((s32)R(rs) < 0) DelayBranchTo(addr); else PC += 4; break;//bltzal
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case 17: BranchRSZeroComp(op, CC_L, true, false); break; //R(MIPS_REG_RA) = PC + 8; if ((s32)R(rs) >= 0) DelayBranchTo(addr); else PC += 4; break;//bgezal
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case 18: BranchRSZeroComp(op, CC_GE, true, true); break; //R(MIPS_REG_RA) = PC + 8; if ((s32)R(rs) < 0) DelayBranchTo(addr); else SkipLikely(); break;//bltzall
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case 19: BranchRSZeroComp(op, CC_L, true, true); break; //R(MIPS_REG_RA) = PC + 8; if ((s32)R(rs) >= 0) DelayBranchTo(addr); else SkipLikely(); break;//bgezall
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default:
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_dbg_assert_msg_(CPU,0,"Trying to compile instruction that can't be compiled");
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break;
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}
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}
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// If likely is set, discard the branch slot if NOT taken.
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void Jit::BranchFPFlag(MIPSOpcode op, Gen::CCFlags cc, bool likely)
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{
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CONDITIONAL_LOG;
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if (js.inDelaySlot) {
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ERROR_LOG_REPORT(JIT, "Branch in FPFlag delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
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return;
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}
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int offset = _IMM16 << 2;
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u32 targetAddr = js.compilerPC + offset + 4;
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MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4);
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bool delaySlotIsNice = IsDelaySlotNiceFPU(op, delaySlotOp);
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CONDITIONAL_NICE_DELAYSLOT;
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if (!likely && delaySlotIsNice)
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CompileDelaySlot(DELAYSLOT_NICE);
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TEST(32, M((void *)&(mips_->fpcond)), Imm32(1));
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CompBranchExits(cc, targetAddr, js.compilerPC + 8, delaySlotIsNice, likely, false);
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}
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void Jit::Comp_FPUBranch(MIPSOpcode op)
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{
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switch((op >> 16) & 0x1f)
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{
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case 0: BranchFPFlag(op, CC_NZ, false); break; //bc1f
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case 1: BranchFPFlag(op, CC_Z, false); break; //bc1t
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case 2: BranchFPFlag(op, CC_NZ, true); break; //bc1fl
|
|
case 3: BranchFPFlag(op, CC_Z, true); break; //bc1tl
|
|
default:
|
|
_dbg_assert_msg_(CPU,0,"Trying to interpret instruction that can't be interpreted");
|
|
break;
|
|
}
|
|
}
|
|
|
|
// If likely is set, discard the branch slot if NOT taken.
|
|
void Jit::BranchVFPUFlag(MIPSOpcode op, Gen::CCFlags cc, bool likely)
|
|
{
|
|
CONDITIONAL_LOG;
|
|
if (js.inDelaySlot) {
|
|
ERROR_LOG_REPORT(JIT, "Branch in VFPU delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
|
|
return;
|
|
}
|
|
int offset = _IMM16 << 2;
|
|
u32 targetAddr = js.compilerPC + offset + 4;
|
|
|
|
MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4);
|
|
|
|
// Sometimes there's a VFPU branch in a delay slot (Disgaea 2: Dark Hero Days, Zettai Hero Project, La Pucelle)
|
|
// The behavior is undefined - the CPU may take the second branch even if the first one passes.
|
|
// However, it does consistently try each branch, which these games seem to expect.
|
|
bool delaySlotIsBranch = MIPSCodeUtils::IsVFPUBranch(delaySlotOp);
|
|
bool delaySlotIsNice = !delaySlotIsBranch && IsDelaySlotNiceVFPU(op, delaySlotOp);
|
|
CONDITIONAL_NICE_DELAYSLOT;
|
|
if (!likely && delaySlotIsNice)
|
|
CompileDelaySlot(DELAYSLOT_NICE);
|
|
if (delaySlotIsBranch && (signed short)(delaySlotOp & 0xFFFF) != (signed short)(op & 0xFFFF) - 1)
|
|
ERROR_LOG_REPORT(JIT, "VFPU branch in VFPU delay slot at %08x with different target %d / %d", js.compilerPC, (signed short)(delaySlotOp & 0xFFFF), (signed short)(op & 0xFFFF) - 1);
|
|
|
|
// THE CONDITION
|
|
int imm3 = (op >> 18) & 7;
|
|
|
|
TEST(32, M((void *)&(mips_->vfpuCtrl[VFPU_CTRL_CC])), Imm32(1 << imm3));
|
|
|
|
u32 notTakenTarget = js.compilerPC + (delaySlotIsBranch ? 4 : 8);
|
|
CompBranchExits(cc, targetAddr, notTakenTarget, delaySlotIsNice, likely, false);
|
|
}
|
|
|
|
|
|
void Jit::Comp_VBranch(MIPSOpcode op)
|
|
{
|
|
switch ((op >> 16) & 3)
|
|
{
|
|
case 0: BranchVFPUFlag(op, CC_NZ, false); break; //bvf
|
|
case 1: BranchVFPUFlag(op, CC_Z, false); break; //bvt
|
|
case 2: BranchVFPUFlag(op, CC_NZ, true); break; //bvfl
|
|
case 3: BranchVFPUFlag(op, CC_Z, true); break; //bvtl
|
|
default:
|
|
_dbg_assert_msg_(CPU,0,"Comp_VBranch: Invalid instruction");
|
|
break;
|
|
}
|
|
}
|
|
|
|
void Jit::Comp_Jump(MIPSOpcode op)
|
|
{
|
|
CONDITIONAL_LOG;
|
|
if (js.inDelaySlot) {
|
|
ERROR_LOG_REPORT(JIT, "Branch in Jump delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
|
|
return;
|
|
}
|
|
u32 off = _IMM26 << 2;
|
|
u32 targetAddr = (js.compilerPC & 0xF0000000) | off;
|
|
|
|
// Might be a stubbed address or something?
|
|
if (!Memory::IsValidAddress(targetAddr))
|
|
{
|
|
if (js.nextExit == 0)
|
|
ERROR_LOG_REPORT(JIT, "Jump to invalid address: %08x", targetAddr)
|
|
else
|
|
js.compiling = false;
|
|
// TODO: Mark this block dirty or something? May be indication it will be changed by imports.
|
|
return;
|
|
}
|
|
|
|
switch (op >> 26)
|
|
{
|
|
case 2: //j
|
|
CompileDelaySlot(DELAYSLOT_NICE);
|
|
if (jo.continueJumps && js.numInstructions < jo.continueMaxInstructions)
|
|
{
|
|
// Account for the increment in the loop.
|
|
js.compilerPC = targetAddr - 4;
|
|
// In case the delay slot was a break or something.
|
|
js.compiling = true;
|
|
return;
|
|
}
|
|
FlushAll();
|
|
CONDITIONAL_LOG_EXIT(targetAddr);
|
|
WriteExit(targetAddr, js.nextExit++);
|
|
break;
|
|
|
|
case 3: //jal
|
|
// Special case for branches to "replace functions":
|
|
if (ReplaceJalTo(targetAddr))
|
|
return;
|
|
|
|
// Save return address - might be overwritten by delay slot.
|
|
gpr.SetImm(MIPS_REG_RA, js.compilerPC + 8);
|
|
CompileDelaySlot(DELAYSLOT_NICE);
|
|
if (jo.continueJumps && js.numInstructions < jo.continueMaxInstructions)
|
|
{
|
|
// Account for the increment in the loop.
|
|
js.compilerPC = targetAddr - 4;
|
|
// In case the delay slot was a break or something.
|
|
js.compiling = true;
|
|
return;
|
|
}
|
|
FlushAll();
|
|
CONDITIONAL_LOG_EXIT(targetAddr);
|
|
WriteExit(targetAddr, js.nextExit++);
|
|
break;
|
|
|
|
default:
|
|
_dbg_assert_msg_(CPU,0,"Trying to compile instruction that can't be compiled");
|
|
break;
|
|
}
|
|
js.compiling = false;
|
|
}
|
|
|
|
static u32 savedPC;
|
|
|
|
void Jit::Comp_JumpReg(MIPSOpcode op)
|
|
{
|
|
CONDITIONAL_LOG;
|
|
if (js.inDelaySlot) {
|
|
ERROR_LOG_REPORT(JIT, "Branch in JumpReg delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
|
|
return;
|
|
}
|
|
MIPSGPReg rs = _RS;
|
|
MIPSGPReg rd = _RD;
|
|
bool andLink = (op & 0x3f) == 9;
|
|
|
|
MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4);
|
|
bool delaySlotIsNice = IsDelaySlotNiceReg(op, delaySlotOp, rs);
|
|
if (andLink && rs == rd)
|
|
delaySlotIsNice = false;
|
|
CONDITIONAL_NICE_DELAYSLOT;
|
|
|
|
if (IsSyscall(delaySlotOp))
|
|
{
|
|
// If this is a syscall, write the pc (for thread switching and other good reasons.)
|
|
gpr.MapReg(rs, true, false);
|
|
MOV(32, M(¤tMIPS->pc), gpr.R(rs));
|
|
if (andLink)
|
|
gpr.SetImm(rd, js.compilerPC + 8);
|
|
CompileDelaySlot(DELAYSLOT_FLUSH);
|
|
|
|
// Syscalls write the exit code for us.
|
|
_dbg_assert_msg_(JIT, !js.compiling, "Expected syscall to write an exit code.");
|
|
return;
|
|
}
|
|
else if (delaySlotIsNice)
|
|
{
|
|
if (andLink)
|
|
gpr.SetImm(rd, js.compilerPC + 8);
|
|
CompileDelaySlot(DELAYSLOT_NICE);
|
|
|
|
if (!andLink && rs == MIPS_REG_RA && g_Config.bDiscardRegsOnJRRA) {
|
|
// According to the MIPS ABI, there are some regs we don't need to preserve.
|
|
// Let's discard them so we don't need to write them back.
|
|
// NOTE: Not all games follow the MIPS ABI! Tekken 6, for example, will crash
|
|
// with this enabled.
|
|
gpr.DiscardRegContentsIfCached(MIPS_REG_COMPILER_SCRATCH);
|
|
for (int i = MIPS_REG_A0; i <= MIPS_REG_T7; i++)
|
|
gpr.DiscardRegContentsIfCached((MIPSGPReg)i);
|
|
gpr.DiscardRegContentsIfCached(MIPS_REG_T8);
|
|
gpr.DiscardRegContentsIfCached(MIPS_REG_T9);
|
|
}
|
|
|
|
if (jo.continueJumps && gpr.IsImm(rs) && js.numInstructions < jo.continueMaxInstructions)
|
|
{
|
|
// Account for the increment in the loop.
|
|
js.compilerPC = gpr.GetImm(rs) - 4;
|
|
// In case the delay slot was a break or something.
|
|
js.compiling = true;
|
|
return;
|
|
}
|
|
|
|
MOV(32, R(EAX), gpr.R(rs));
|
|
FlushAll();
|
|
}
|
|
else
|
|
{
|
|
// Latch destination now - save it in memory.
|
|
gpr.MapReg(rs, true, false);
|
|
MOV(32, M(&savedPC), gpr.R(rs));
|
|
if (andLink)
|
|
gpr.SetImm(rd, js.compilerPC + 8);
|
|
CompileDelaySlot(DELAYSLOT_NICE);
|
|
MOV(32, R(EAX), M(&savedPC));
|
|
FlushAll();
|
|
}
|
|
|
|
switch (op & 0x3f)
|
|
{
|
|
case 8: //jr
|
|
break;
|
|
case 9: //jalr
|
|
break;
|
|
default:
|
|
_dbg_assert_msg_(CPU,0,"Trying to compile instruction that can't be compiled");
|
|
break;
|
|
}
|
|
|
|
CONDITIONAL_LOG_EXIT_EAX();
|
|
WriteExitDestInEAX();
|
|
js.compiling = false;
|
|
}
|
|
|
|
void Jit::Comp_Syscall(MIPSOpcode op)
|
|
{
|
|
// TODO: Maybe discard v0, v1, and some temps? Definitely at?
|
|
FlushAll();
|
|
|
|
// If we're in a delay slot, this is off by one.
|
|
const int offset = js.inDelaySlot ? -1 : 0;
|
|
WriteDowncount(offset);
|
|
js.downcountAmount = -offset;
|
|
|
|
// Skip the CallSyscall where possible.
|
|
void *quickFunc = GetQuickSyscallFunc(op);
|
|
if (quickFunc)
|
|
ABI_CallFunctionP(quickFunc, (void *)GetSyscallInfo(op));
|
|
else
|
|
ABI_CallFunctionC((void *)&CallSyscall, op.encoding);
|
|
|
|
WriteSyscallExit();
|
|
js.compiling = false;
|
|
}
|
|
|
|
void Jit::Comp_Break(MIPSOpcode op)
|
|
{
|
|
Comp_Generic(op);
|
|
WriteSyscallExit();
|
|
js.compiling = false;
|
|
}
|
|
|
|
} // namespace Mipscomp
|