mirror of
https://github.com/hrydgard/ppsspp.git
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256 lines
8.1 KiB
C++
256 lines
8.1 KiB
C++
// Copyright (c) 2023- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include "Common/Log.h"
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#include "Core/CoreTiming.h"
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#include "Core/MemMap.h"
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#include "Core/MIPS/RiscV/RiscVJit.h"
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#include "Core/MIPS/RiscV/RiscVRegCache.h"
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#include "Core/MIPS/JitCommon/JitCommon.h"
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#include "Core/MIPS/JitCommon/JitState.h"
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#include "Core/Core.h"
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namespace MIPSComp {
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using namespace RiscVGen;
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using namespace RiscVJitConstants;
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static const bool enableDebug = false;
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static const bool enableDisasm = false;
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static void ShowPC(u32 downcount, void *membase, void *jitbase) {
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static int count = 0;
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if (currentMIPS) {
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ERROR_LOG(Log::JIT, "[%08x] ShowPC Downcount : %08x %d %p %p", currentMIPS->pc, downcount, count, membase, jitbase);
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} else {
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ERROR_LOG(Log::JIT, "Universe corrupt?");
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}
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//if (count > 2000)
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// exit(0);
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count++;
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}
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void RiscVJitBackend::GenerateFixedCode(MIPSState *mipsState) {
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// This will be used as a writable scratch area, always 32-bit accessible.
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const u8 *start = AlignCodePage();
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if (DebugProfilerEnabled()) {
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ProtectMemoryPages(start, GetMemoryProtectPageSize(), MEM_PROT_READ | MEM_PROT_WRITE);
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hooks_.profilerPC = (uint32_t *)GetWritableCodePtr();
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*hooks_.profilerPC = 0;
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hooks_.profilerStatus = (IRProfilerStatus *)GetWritableCodePtr() + 1;
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*hooks_.profilerStatus = IRProfilerStatus::NOT_RUNNING;
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SetCodePointer(GetCodePtr() + sizeof(uint32_t) * 2, GetWritableCodePtr() + sizeof(uint32_t) * 2);
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}
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const u8 *disasmStart = AlignCodePage();
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BeginWrite(GetMemoryProtectPageSize());
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if (jo.useStaticAlloc) {
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saveStaticRegisters_ = AlignCode16();
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SW(DOWNCOUNTREG, CTXREG, offsetof(MIPSState, downcount));
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regs_.EmitSaveStaticRegisters();
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RET();
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loadStaticRegisters_ = AlignCode16();
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regs_.EmitLoadStaticRegisters();
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LW(DOWNCOUNTREG, CTXREG, offsetof(MIPSState, downcount));
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RET();
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} else {
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saveStaticRegisters_ = nullptr;
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loadStaticRegisters_ = nullptr;
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}
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applyRoundingMode_ = AlignCode16();
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{
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// Not sure if RISC-V has any flush to zero capability? Leaving it off for now...
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LWU(SCRATCH2, CTXREG, offsetof(MIPSState, fcr31));
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// We can skip if the rounding mode is nearest (0) and flush is not set.
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// (as restoreRoundingMode cleared it out anyway)
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FixupBranch skip = BEQ(SCRATCH2, R_ZERO);
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// MIPS Rounding Mode: RISC-V
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// 0: Round nearest 0
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// 1: Round to zero 1
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// 2: Round up (ceil) 3
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// 3: Round down (floor) 2
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if (cpu_info.RiscV_Zbs) {
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BEXTI(SCRATCH1, SCRATCH2, 1);
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} else {
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ANDI(SCRATCH1, SCRATCH2, 2);
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SRLI(SCRATCH1, SCRATCH1, 1);
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}
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// Swap the lowest bit by the second bit.
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XOR(SCRATCH2, SCRATCH2, SCRATCH1);
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FSRM(SCRATCH2);
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SetJumpTarget(skip);
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RET();
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}
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hooks_.enterDispatcher = (IRNativeFuncNoArg)AlignCode16();
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// Start by saving some regs on the stack. There are 12 GPs and 12 FPs we want.
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// Note: we leave R_SP as, well, SP, so it doesn't need to be saved.
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_assert_msg_(cpu_info.Mode64bit, "RiscVAsm currently assumes RV64, not RV32 or RV128");
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static constexpr RiscVReg regs_to_save[]{ R_RA, X8, X9, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27 };
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// TODO: Maybe we shouldn't regalloc all of these? Is it worth it?
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static constexpr RiscVReg regs_to_save_fp[]{ F8, F9, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27 };
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int saveSize = (XLEN / 8) * (int)(ARRAY_SIZE(regs_to_save) + ARRAY_SIZE(regs_to_save_fp));
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if (saveSize & 0xF)
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saveSize += 8;
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_assert_msg_((saveSize & 0xF) == 0, "Stack must be kept aligned");
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int saveOffset = 0;
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ADDI(R_SP, R_SP, -saveSize);
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for (RiscVReg r : regs_to_save) {
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SD(r, R_SP, saveOffset);
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saveOffset += XLEN / 8;
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}
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for (RiscVReg r : regs_to_save_fp) {
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FS(64, r, R_SP, saveOffset);
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saveOffset += XLEN / 8;
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}
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_assert_(saveOffset <= saveSize);
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// Fixed registers, these are always kept when in Jit context.
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LI(MEMBASEREG, Memory::base, SCRATCH1);
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LI(CTXREG, mipsState, SCRATCH1);
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LI(JITBASEREG, GetBasePtr() - MIPS_EMUHACK_OPCODE, SCRATCH1);
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LoadStaticRegisters();
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WriteDebugProfilerStatus(IRProfilerStatus::IN_JIT);
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MovFromPC(SCRATCH1);
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WriteDebugPC(SCRATCH1);
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outerLoopPCInSCRATCH1_ = GetCodePtr();
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MovToPC(SCRATCH1);
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outerLoop_ = GetCodePtr();
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// Advance can change the downcount (or thread), so must save/restore around it.
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SaveStaticRegisters();
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RestoreRoundingMode(true);
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WriteDebugProfilerStatus(IRProfilerStatus::TIMER_ADVANCE);
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QuickCallFunction(&CoreTiming::Advance, X7);
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WriteDebugProfilerStatus(IRProfilerStatus::IN_JIT);
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ApplyRoundingMode(true);
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LoadStaticRegisters();
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dispatcherCheckCoreState_ = GetCodePtr();
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LI(SCRATCH1, &coreState, SCRATCH2);
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LW(SCRATCH1, SCRATCH1, 0);
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FixupBranch badCoreState = BNE(SCRATCH1, R_ZERO);
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// We just checked coreState, so go to advance if downcount is negative.
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BLT(DOWNCOUNTREG, R_ZERO, outerLoop_);
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FixupBranch skipToRealDispatch = J();
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dispatcherPCInSCRATCH1_ = GetCodePtr();
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MovToPC(SCRATCH1);
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hooks_.dispatcher = GetCodePtr();
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FixupBranch bail = BLT(DOWNCOUNTREG, R_ZERO);
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SetJumpTarget(skipToRealDispatch);
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dispatcherNoCheck_ = GetCodePtr();
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// Debug
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if (enableDebug) {
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MV(X10, DOWNCOUNTREG);
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MV(X11, MEMBASEREG);
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MV(X12, JITBASEREG);
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QuickCallFunction(&ShowPC, X7);
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}
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LWU(SCRATCH1, CTXREG, offsetof(MIPSState, pc));
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WriteDebugPC(SCRATCH1);
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#ifdef MASKED_PSP_MEMORY
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LI(SCRATCH2, 0x3FFFFFFF);
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AND(SCRATCH1, SCRATCH1, SCRATCH2);
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#endif
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ADD(SCRATCH1, SCRATCH1, MEMBASEREG);
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hooks_.dispatchFetch = GetCodePtr();
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LWU(SCRATCH1, SCRATCH1, 0);
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SRLI(SCRATCH2, SCRATCH1, 24);
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// We're in other words comparing to the top 8 bits of MIPS_EMUHACK_OPCODE by subtracting.
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ADDI(SCRATCH2, SCRATCH2, -(MIPS_EMUHACK_OPCODE >> 24));
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FixupBranch needsCompile = BNE(SCRATCH2, R_ZERO);
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// No need to mask, JITBASEREG has already accounted for the upper bits.
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ADD(SCRATCH1, JITBASEREG, SCRATCH1);
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JR(SCRATCH1);
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SetJumpTarget(needsCompile);
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// No block found, let's jit. We don't need to save static regs, they're all callee saved.
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RestoreRoundingMode(true);
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WriteDebugProfilerStatus(IRProfilerStatus::COMPILING);
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QuickCallFunction(&MIPSComp::JitAt, X7);
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WriteDebugProfilerStatus(IRProfilerStatus::IN_JIT);
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ApplyRoundingMode(true);
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// Try again, the block index should be set now.
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J(dispatcherNoCheck_);
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SetJumpTarget(bail);
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LI(SCRATCH1, &coreState, SCRATCH2);
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LW(SCRATCH1, SCRATCH1, 0);
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BEQ(SCRATCH1, R_ZERO, outerLoop_);
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const uint8_t *quitLoop = GetCodePtr();
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SetJumpTarget(badCoreState);
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WriteDebugProfilerStatus(IRProfilerStatus::NOT_RUNNING);
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SaveStaticRegisters();
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RestoreRoundingMode(true);
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_assert_msg_(cpu_info.Mode64bit, "RiscVAsm currently assumes RV64, not RV32 or RV128");
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saveOffset = 0;
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for (RiscVReg r : regs_to_save) {
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LD(r, R_SP, saveOffset);
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saveOffset += XLEN / 8;
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}
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for (RiscVReg r : regs_to_save_fp) {
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FL(64, r, R_SP, saveOffset);
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saveOffset += XLEN / 8;
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}
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ADDI(R_SP, R_SP, saveSize);
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RET();
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hooks_.crashHandler = GetCodePtr();
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LI(SCRATCH1, &coreState, SCRATCH2);
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LI(SCRATCH2, CORE_RUNTIME_ERROR);
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SW(SCRATCH2, SCRATCH1, 0);
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J(quitLoop);
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// Leave this at the end, add more stuff above.
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if (enableDisasm) {
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#if PPSSPP_ARCH(RISCV64)
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std::vector<std::string> lines = DisassembleRV64(start, GetCodePtr() - start);
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for (auto s : lines) {
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INFO_LOG(Log::JIT, "%s", s.c_str());
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}
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#endif
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}
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// Let's spare the pre-generated code from unprotect-reprotect.
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AlignCodePage();
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jitStartOffset_ = (int)(GetCodePtr() - start);
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// Don't forget to zap the instruction cache! This must stay at the end of this function.
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FlushIcache();
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EndWrite();
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}
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} // namespace MIPSComp
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