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9243 commits

Author SHA1 Message Date
Unknown W. Brackets
f9863c3be2 Mp3: Align CheckStreamDataNeeded with InfoToAdd. 
May cause problems if they don't match.
 2019-04-23 20:42:13 -07:00
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f1eaf9dc0e Mp3: Don't change buffer accounting until add. 
If we just ask what we should add, that is meant to stay static until we
do actually add it.

This also reduces the max we ask for at a time, which better matches
correct behavior and might impact game behavior.
 2019-04-23 20:18:16 -07:00
Unknown W. Brackets
709c9dc93c Mp3: Fix errors on sceMp3NotifyAddStreamData. 2019-04-23 19:48:01 -07:00
Unknown W. Brackets
5b9a3e6ca8 Mp3: Improve handle releasing behavior. 2019-04-22 23:01:40 -07:00
Unknown W. Brackets
4563d9487b Mp3: Better errors in sceMp3GetInfoToAddStreamData. 2019-04-22 22:57:05 -07:00
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351a10bd69 Mp3: Allow allocating two mp3 handles. 
The handles are always 0 or 1, not pointers, which might be relied upon by
some games.  Two could be used with the same pointer.

This also makes NULL a valid pointer, which is used for low level mp3s.
 2019-04-21 22:28:04 -07:00
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4ae2108629 Mp3: Fail to reserve if resource not inited. 
Also, add a required parameter for sceMp3LowLevelInit, since it fails
unless proper values are passed for this on a PSP.
 2019-04-21 19:54:34 -07:00
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92829d47fd Mp3: Better match resched on resource init/term. 
It always seems to return 0, though.
 2019-04-21 18:22:56 -07:00
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8d4ab57b46 Oops, got these backwards. 
Surprising this didn't break as much as expected.  Mostly broke the 60 FPS
limit hack.
 2019-04-16 17:36:29 -07:00
Henrik Rydgård
dcd2ff03b0
Merge pull request #11971 from unknownbrackets/power 
Correct cpu/pll/bus hz update and rescheduling
 2019-04-16 09:41:43 +02:00
M4xw
b9352354c9 Masked PSP Memory support for the AArch64 Dynarec 2019-04-15 12:07:57 +02:00
Unknown W. Brackets
ad299ca92d Power: Match reschedule timing better. 2019-04-14 15:06:32 -07:00
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bc4a203fcf Power: Correct hz on update and improve resched. 
It only reschedules when the PLL changes, which changes in steps.  This
also reads back much more accurate Mhz for each of PLL, CPU, and bus.
 2019-04-14 14:51:35 -07:00
Unknown W. Brackets
ec7cffa847 interp: Handle vtfm/vhtfm prefixes properly. 2019-04-02 18:46:39 -07:00
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442d6450bb interp: Correct prefixes on vfad and vavg. 
Including write mask, which didn't work before.
 2019-04-02 18:46:39 -07:00
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5414c12a15 interp: Cleanup prefix/size in vcrsp/vqmul. 2019-04-02 07:12:34 -07:00
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58573cd4b4 interp: Handle invalid swizzle for vmin/vmax. 2019-04-02 07:08:33 -07:00
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e8c060bb5f interp: Correct vwbn and vlgb size behavior. 2019-04-02 07:08:20 -07:00
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89dbfd7d5b interp: Better prefixes for vdiv/similar ops. 
Turns out it does work, just uses the wrong slot like S/T after all.
These other ops must go through the a similar process.
 2019-04-02 07:07:53 -07:00
Henrik Rydgård
24cfad87d1
Merge pull request #11955 from unknownbrackets/vfpu-chunk6 
Correct prefixes for several swizzled ops, use zero for invalid
 2019-04-01 17:13:34 +02:00
Henrik Rydgård
b346142df8
Merge pull request #11954 from unknownbrackets/vfpu-chunk5 
Fix prefix and size handling for vsbx, vsocp, and integer conv ops
 2019-04-01 17:12:03 +02:00
Unknown W. Brackets
6f87987e7b interp: Correct prefixes on vdot/vhdp. 2019-03-31 17:12:21 -07:00
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b24f84d1a2 interp: Handle prefixes on matrix init ops. 2019-03-31 17:11:24 -07:00
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59905de719 interp: Correct vsgn out of swizzle bounds. 2019-03-31 17:10:51 -07:00
Unknown W. Brackets
85ff32eed1 interp: Handle vsgn prefixing. 
One could compare against 3 using this, it just generates zeros to compare
with.
 2019-03-31 17:10:51 -07:00
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a5214d0b1a Jit: Ignore high bit in vmfvc/vmtvc. 2019-03-31 17:09:55 -07:00
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b881a689c4 interp: Ignore high bit in vmfvc/vmtvc. 
Both 0 and 128 read/write the S prefix, for example.
 2019-03-31 17:09:55 -07:00
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dffa238611 interp: Handle invalid swizzle in vsge/vslt. 2019-03-31 15:05:43 -07:00
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dfd8094f21 interp: Implement vcrs prefixes and sizes. 
It only makes sense as triple, but it can be used as quad/single/etc. and
has consistent and sane results.
 2019-03-31 15:05:15 -07:00
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fa7ac7bc64 interp: Correct simple vmov variant prefixing. 2019-03-31 15:01:28 -07:00
Unknown W. Brackets
01aebe54b9 interp: Correct vdet prefix handling. 2019-03-31 15:01:11 -07:00
Unknown W. Brackets
cc58d0d3a3 interp: Correct prefixes in vsrt ops. 2019-03-31 15:00:12 -07:00
Unknown W. Brackets
f2be0cb083 interp: Correct prefixes for vsbn/vsbz. 2019-03-31 13:52:59 -07:00
Unknown W. Brackets
175ceef583 interp: Cleanup vsocp size handling. 2019-03-31 13:52:07 -07:00
Unknown W. Brackets
4a2f8a74dc interp: Correct size handling for vi2x ops. 2019-03-31 13:51:12 -07:00
Unknown W. Brackets
b75690787e interp: Correct swizzle on vx2i ops. 2019-03-31 13:51:12 -07:00
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68cdcba6c5 interp: Don't write lane 2 on single colorconv. 
Not that it's valid to use the op with that size anyway.
 2019-03-31 13:51:12 -07:00
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5736b1be2a interp: Correct some negative invalid zero cases. 
In these cases, the input value wires to +0.  Also, transposed the values
in a comment (oops.)
 2019-03-31 13:45:37 -07:00
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aa998b815c interp: Force vscmp result of invalid to zero. 
Some other ops do this, but mostly only that do plus or minus.
 2019-03-31 13:41:48 -07:00
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c7e83cd4fa interp: Correct vfim for -inf and similar. 
Was dropping the sign bit before for inf and nan.
 2019-03-31 13:41:48 -07:00
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5749ae09d0 interp: Correct vmfvc register behavior. 
The target and source registers were completely wrong.
 2019-03-31 13:41:48 -07:00
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b2e024025f interp: Handle wrong sizes of vf2h/vh2f. 
Probably not ever used, but they have consistent behavior.
 2019-03-31 13:41:48 -07:00
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aceb0a8244 interp: Correct vrnd prefix handling. 
We don't match random values perfectly anyway, but at least we should vary
at the right times.
 2019-03-31 13:41:48 -07:00
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dfc2449f35 interp: Match actual vdiv prefix handling. 2019-03-31 13:41:48 -07:00
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af3ed69144 interp: Mask moves to vfpu ctrl. 
These bits of the registers can't be written.
 2019-03-31 10:37:07 -07:00
Unknown W. Brackets
2a5d4e577d interp: Handle NAN more correctly in vscmp. 2019-03-31 10:37:07 -07:00
Unknown W. Brackets
db28c61272 interp: Handle flush prefixes slightly better. 2019-03-31 10:37:07 -07:00
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d40ac043d4 interp: Handle prefixes for Vmmov/Vmmul/Vmscl. 
I doubt any actual code uses this, but we have some tricky VFPU bugs left,
so just trying for maximum accuracy in the interpreter.
 2019-03-31 10:37:07 -07:00
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26b1368f7b interp: Handle vrot prefixes mostly correctly. 
Still some issues with 1/2 results and negate on swizzle.
 2019-03-31 10:37:07 -07:00
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8fd8dce185 interp: Use a helper to generate prefix consts. 
This makes more logical sense that using the VFPU_SWIZZLE and VFPU_ABS
macros to select the constant, although that's how the bits work.
 2019-03-31 10:33:26 -07:00