Florent Castelli
8c3552de74
cmake: Detect features at compile time
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Instead of relying on manually passed down flags from CMake,
we now have ppsspp_config.h file to create the platform defines for us.
This improves support for multiplatform builds (such as iOS).
2016-10-19 12:31:19 +02:00
Unknown W. Brackets
2d3df5c621
armjit: Handle divide by zero more accurately.
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Turns out, some games may depend on this behavior.
2016-05-19 00:07:41 -07:00
Unknown W. Brackets
a05ae2a0a6
Correct divide by zero HI/LO values a bit.
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Interpreter is now correct, but it's probably not all that important to
get right in jit.
2016-05-14 19:23:50 -07:00
Henrik Rydgard
dedcc149d8
ARM64: Fix typo in mfhi and mflo instructions. May help #8383
2016-01-19 23:26:43 +01:00
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9262ddfc13
Avoid any possible shifts by 32.
2015-07-19 13:25:50 -07:00
Henrik Rydgard
b73920fcba
ARM64: Cleanups in regcache and jit
2015-07-11 17:00:01 +02:00
Henrik Rydgard
f42f81a4da
ARM64: Optimize small adjustments of pointerified registers
2015-07-11 16:59:11 +02:00
Unknown W. Brackets
db3dffb44d
arm64: Oops, fix flushing zero from an armreg.
2015-07-05 11:57:18 -07:00
Unknown W. Brackets
204c1dc8dd
arm64: Optimize 3ops against zero.
2015-07-05 09:52:53 -07:00
Unknown W. Brackets
66adc4e695
jit: Normalize CONDITIONAL_DISABLE formatting.
2015-07-02 20:31:37 -07:00
Unknown W. Brackets
fed687fb59
arm64: Meld LO and HI together for multiplies.
2015-07-02 20:31:37 -07:00
Unknown W. Brackets
757a1a414a
arm64: Workaround an apparent gcc bug.
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Only seems to happen with unsigned. This took a while to track down...
2015-07-02 19:59:38 -07:00
Unknown W. Brackets
e94fd3d4bd
arm64: Fix div/divu remainders.
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Erp, I transposed the args when I pasted them.
2015-06-28 16:52:49 -07:00
Unknown W. Brackets
81b923f1dc
arm64: Correct movz/movn. Weren't right after all.
2015-06-28 16:49:28 -07:00
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0978aa4d5e
arm64: Use msub for div/divu remainder.
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Not really much faster, but less instructions at least.
2015-06-28 09:05:39 -07:00
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0a5b1c030b
arm64: Implement ext and ins.
2015-06-28 08:45:17 -07:00
Unknown W. Brackets
daddb73f22
arm64: Implement nor.
2015-06-28 00:41:04 -07:00
Unknown W. Brackets
11a851a139
arm64: Enable movz/movn.
2015-06-28 00:41:04 -07:00
Unknown W. Brackets
223e55a453
arm64: Undisable clz/clo, they work.
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Also, avoid a temp in clo. It's the tiniest bit faster on A57, though
we'll see how it works out elsewhere. A bit clearer without the temp
imho.
2015-06-28 00:41:03 -07:00
Unknown W. Brackets
81bc8107cf
arm64: Use UBFX, not LSR, for slti sign check.
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This is about 22% faster on the A57 (for just this one instruction, so not
a huge impact overall.) Makes sense that it would be since not arith.
2015-06-28 00:41:03 -07:00
Henrik Rydgard
8df8c210d1
ARM64: Start porting over VFPU stuff from ARM, fix regalloc bug
2015-04-06 18:13:28 +02:00
Henrik Rydgard
34e61ab875
ARM64: More FPU instructions (int<->float convert), minor stuff
2015-04-06 18:13:25 +02:00
Henrik Rydgard
25ec85551f
ARM64: Implement FP compares, misc
2015-04-06 18:13:22 +02:00
Henrik Rydgard
ceb9f66502
ARM64: Fix bug in mult
2015-04-06 18:13:21 +02:00
Henrik Rydgard
1a02e32ad1
ARM64: Implement the multiplication instructions
2015-04-06 18:13:20 +02:00
Henrik Rydgard
4233921ab7
ARM64: Some more instructions, func replacements
2015-04-06 18:13:16 +02:00
Henrik Rydgard
9e2786b319
ARM64: Fix and enable a bunch more instructions. temporarily disable movz movn
2015-04-06 18:13:15 +02:00
Henrik Rydgard
2bca05c4f2
ARM64: implement shifts, movz/movn. Corresponding fixes to emitter/disasm
2015-04-06 18:13:14 +02:00
Henrik Rydgard
86ff2a2806
ARM64: Enable a bunch of arithmetic instructions that now work, thanks to emitter fixes
2015-04-06 18:13:13 +02:00
Henrik Rydgard
77501e220d
ARM64: Enable a few more instructions, more emitter/disasm unittests
2015-04-06 18:13:13 +02:00
Henrik Rydgard
8dc77ff32e
ARM64: Turn off some debugging stuff, start implementing instructions. Something is wrong though, if I implement more than addiu things break..
2015-04-06 18:13:09 +02:00
Henrik Rydgard
b309c83973
Initial work on ARM64, based on the ARM jit.
2015-04-06 18:13:01 +02:00
