Emulation/ppsspp
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35615 commits 81 branches 122 tags 700 MiB
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32 commits

Author SHA1 Message Date
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a0ef9ce103 riscv: Add half-float encodings. 
These are simple.
 2023-01-29 16:31:01 -08:00
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dcd83c1e47 riscv: Detect Zicsr with cpu_features. 2023-01-29 15:24:41 -08:00
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3bc2450b5e
riscv: Add bitmanip instructions to emitter (#16832) 
* riscv: Cleanup emitter, add bitmanip detect.

Better to encode using Funct7::ZERO, and obviously for SRA.

* riscv: Add bitmanip instructions to emitter.
 2023-01-22 21:37:47 +01:00
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2aeee83971 riscv: Add vector transfer instructions. 2023-01-22 00:17:40 -08:00
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c99eb18f33 riscv: Add vector mask instructions. 2023-01-21 23:43:28 -08:00
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88de043329 riscv: Add vector reduce instructions. 2023-01-21 22:35:38 -08:00
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2a7bdbf802 riscv: Add vector float move/compare/unary. 2023-01-21 22:05:13 -08:00
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f0796676fd riscv: Add vector float arith/mul funcs. 
Including all the fused multiplies.
 2023-01-21 20:48:49 -08:00
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a1ca291362 riscv: Add vector fixed-point arith instructions. 2023-01-21 20:23:10 -08:00
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a313e440b4 riscv: Add vector integer move/broadcast. 2023-01-21 19:46:50 -08:00
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6f78f2a2d2 riscv: Add vector integer muliplies. 2023-01-21 19:46:34 -08:00
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b3be901557 riscv: Add vector bitwise/compare funcs. 2023-01-21 19:36:22 -08:00
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6fa50eaa82 riscv: Add vector int add/sub and many encodings. 2023-01-21 19:36:11 -08:00
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bfd60a67ad riscv: Add vector load/store ops. 2023-01-21 19:36:11 -08:00
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82f0502b4e riscv: Implement CPU feature detection. 2022-12-21 03:12:16 +00:00
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5916b3f3a8 riscv: Fix compile error on clang. 
This also works on gcc.
 2022-12-21 03:07:47 +00:00
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1810692236 Global: Cleanup some type/range checks. 2022-12-10 21:13:37 -08:00
Sprite
0ed86188b0 Fix const pointer conversion error for RISC-V 2022-09-15 23:53:19 +08:00
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08d82ec15b riscv: Emit compressed instructions. 
Includes automatically using compressed, optionally.
 2022-08-27 15:44:19 -07:00
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946080206d riscv: Improve sign reduce/immediate readability. 2022-08-27 15:44:18 -07:00
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c807d459f6 riscv: Emit ADD/SUB/etc. for ADDW/SUBW/etc. on R32. 
No need to complicate code, we can just write ADDW() and expect it to work
on R32 (if ever motivated to support it.)
 2022-08-27 15:44:18 -07:00
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c81d887a86 riscv: Include an LI helper in the emitter. 
Can be used for integers and floats.
 2022-08-27 15:44:18 -07:00
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4a93647acb riscv: Emit CSR manipulation instructions. 2022-08-25 21:20:49 -07:00
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b5755b6cf7 riscv: Validate FixupBranch usage better. 
Also avoid FixupBranch alignment issues.
 2022-08-25 21:20:49 -07:00
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591de6be1d riscv: Emit float instructions. 2022-08-25 21:19:28 -07:00
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53693072d2 riscv: Emit atomic operations. 2022-08-25 21:19:28 -07:00
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c66d02d4db riscv: Emit mul/div instructions. 2022-08-25 21:19:28 -07:00
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00280ab2ad riscv: Emit fence and 64-bit instructions. 2022-08-25 21:19:28 -07:00
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49ec8a207d riscv: Emit 32-bit 3-op instructions, validate GPR. 2022-08-25 21:19:27 -07:00
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1c35cfb325 riscv: Emit 32-bit load/store and imm ops. 2022-08-25 21:19:27 -07:00
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1dab9d1875 riscv: Emit standard B/U/J type ops. 2022-08-25 21:19:27 -07:00
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9fcad83940 riscv: Add initial emitter shell. 2022-08-25 21:17:11 -07:00