Unknown W. Brackets
|
5736b1be2a
|
interp: Correct some negative invalid zero cases.
In these cases, the input value wires to +0. Also, transposed the values
in a comment (oops.)
|
2019-03-31 13:45:37 -07:00 |
|
Unknown W. Brackets
|
af3ed69144
|
interp: Mask moves to vfpu ctrl.
These bits of the registers can't be written.
|
2019-03-31 10:37:07 -07:00 |
|
Unknown W. Brackets
|
26b1368f7b
|
interp: Handle vrot prefixes mostly correctly.
Still some issues with 1/2 results and negate on swizzle.
|
2019-03-31 10:37:07 -07:00 |
|
Unknown W. Brackets
|
8fd8dce185
|
interp: Use a helper to generate prefix consts.
This makes more logical sense that using the VFPU_SWIZZLE and VFPU_ABS
macros to select the constant, although that's how the bits work.
|
2019-03-31 10:33:26 -07:00 |
|
Unknown W. Brackets
|
0be3213151
|
interp: Correct vscl prefix handling.
|
2019-03-31 10:13:28 -07:00 |
|
Unknown W. Brackets
|
fef8e71b8f
|
interp: Correct behavior for matrixes with size=1.
Games don't (shouldn't?) actually use 1x1 matrices, but they seem to have
predictable behavior in matrix ops.
|
2019-03-31 08:21:29 -07:00 |
|
Unknown W. Brackets
|
22940f0393
|
Debugger: Avoid asserts in disassembly.
|
2018-06-08 06:59:18 -07:00 |
|
Unknown W. Brackets
|
5b7bd8155d
|
Special case specific sin/cos result values.
Fixes #7737, thanks go to gid15 from Jpcsp for finding and daniel229 for
reporting.
|
2016-05-29 08:51:38 -07:00 |
|
Unknown W. Brackets
|
3f0fc2d851
|
jit-ir: Fix FSat0_1 behavior on -0.0f.
|
2016-05-15 13:10:49 -07:00 |
|
Henrik Rydgard
|
45efcda6b1
|
IR: Some more VFPU
|
2016-05-10 21:50:08 +02:00 |
|
Henrik Rydgard
|
37413f8119
|
We can use sincosf again on Android - the bug in the NDK has been fixed.
|
2014-12-07 11:53:46 +01:00 |
|
Henrik Rydgard
|
8f016d3e48
|
Merge some matrix utils and stuff from the NEON branch
|
2014-11-29 11:37:45 +01:00 |
|
Henrik Rydgard
|
ee1d16cb1d
|
Use sincosf where available (linux)
|
2014-06-15 12:06:02 +02:00 |
|
Henrik Rydgard
|
e6f55bfef0
|
Fix silly mistake in vfpu_sincos. Add unittest.
|
2014-06-15 11:51:30 +02:00 |
|
Henrik Rydgard
|
0879d76503
|
VFPU: Ensure that sin(4*x) returns 0.0 (and cos 1) for all x. Fixes #2921
|
2014-06-15 11:03:00 +02:00 |
|
lioncash
|
b9886942a7
|
Fix some vertical alignments in misc Core source files.
|
2014-03-03 11:16:53 -05:00 |
|
Unknown W. Brackets
|
ec05146ffd
|
Improve vfpu disasm for a few instructions.
|
2013-11-29 10:07:15 -08:00 |
|
Unknown W. Brackets
|
109ad17ac6
|
Use a typesafe struct for opcodes.
Also, correctly read delayslots using Read_Instruction on ARM.
|
2013-08-24 15:36:24 -07:00 |
|
Henrik Rydgard
|
59644ad59b
|
Jit: Implement VMMUL for ARM, optimize the x86 implementation. Also add VCST.
|
2013-07-28 12:14:35 +02:00 |
|
Unknown W. Brackets
|
b733bc1a2a
|
Clean up some indents, add some reporting.
|
2013-05-18 02:09:32 -07:00 |
|
Henrik Rydgard
|
aabc0aa9ef
|
Quick implementation of LV.Q and SV.Q in x86/x64 JIT
|
2013-01-25 19:50:30 +01:00 |
|
Henrik Rydgard
|
64cc573703
|
Switch to "GPL 2.0 or later" for various reasons. I wrote most of the code I imported from Dolphin (which is GPL2-but-not-later), so it should be OK.
|
2012-11-04 23:24:00 +01:00 |
|
Henrik Rydgard
|
4f7ad15758
|
Add snapshot of the whole source code.
|
2012-11-01 16:19:01 +01:00 |
|