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44 commits

Author SHA1 Message Date
Henrik Rydgård
8642134419 VFPU-Int: Add a few fast-paths to ReadMatrix/WriteMatrix. Should gain back part of the speed lost in #12217 
(which fixed #5399).
 2019-08-06 16:29:58 +02:00
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c1c869df27 interp: Implement software inverse square root. 2019-08-04 21:24:13 -07:00
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6028b79895 interp: Oops, fix vdot bug with subnormals. 2019-08-04 21:23:19 -07:00
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13278dc1f4 interp: Implement software sqrt to match PSP. 
This matches the PSP's square root better.

Disabled by default using a compile-time flag.
 2019-08-04 21:23:04 -07:00
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7b84be1479 interp: Fix adding infinity in software dot. 2019-08-04 21:17:34 -07:00
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c61a24cef0 interp: Handle rounding in software dot. 2019-08-04 21:17:27 -07:00
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d5e572b82e interp: Correct INF * 0 during dot. 2019-08-04 21:17:21 -07:00
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2ba35c6391 interp: Use an integer multiply for dots. 2019-08-04 21:17:09 -07:00
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08a894abde interp: Handle NaN better in vfpu_dot. 2019-08-04 21:17:00 -07:00
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4bff980d34 interp: Use software dot for better accuracy. 
This gets some vdot/similar tests to give more accurate results compared
to hardware.  Also added flushing of zero and NaNs.

Currently disabled, only enabled with a compile-time flag.
 2019-08-04 21:14:23 -07:00
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c7e83cd4fa interp: Correct vfim for -inf and similar. 
Was dropping the sign bit before for inf and nan.
 2019-03-31 13:41:48 -07:00
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af3ed69144 interp: Mask moves to vfpu ctrl. 
These bits of the registers can't be written.
 2019-03-31 10:37:07 -07:00
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b86a6af364 interp: Properly apply mask on single lane ops. 
When using something like vadd.s, we should still be applying the mask.
Mainly should only matter if masks are set in a conditional, or if games
nop out instructions.
 2019-03-31 10:13:28 -07:00
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0be3213151 interp: Correct vscl prefix handling. 2019-03-31 10:13:28 -07:00
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fef8e71b8f interp: Correct behavior for matrixes with size=1. 
Games don't (shouldn't?) actually use 1x1 matrices, but they seem to have
predictable behavior in matrix ops.
 2019-03-31 08:21:29 -07:00
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22940f0393 Debugger: Avoid asserts in disassembly. 2018-06-08 06:59:18 -07:00
Henrik Rydgard
e1e335885c A better alternative to #8564 2016-12-01 18:23:58 +01:00
Henrik Rydgard
3cae60b320 Revert potentially dangerous optimization that may have caused #8754, though not sure how. 2016-05-18 21:22:08 +02:00
Henrik Rydgard
2cbfb192c4 IR: Lots more VFPU support, some with SIMD 2016-05-12 12:17:25 +02:00
Bovine
2ed4c1bd6b Fix matrix disassembly notation 
Changed disassembler output to match gas input for operations on
transposed matrices where row != col.
 2015-01-03 02:04:08 -07:00
Henrik Rydgard
29dcc0a303 Minor cleanups, warning fixes 2014-12-06 12:25:28 +01:00
Henrik Rydgard
8f016d3e48 Merge some matrix utils and stuff from the NEON branch 2014-11-29 11:37:45 +01:00
Aapo Rantalainen
ed6b8e34ab Fix missing includes (stdio.h) 2014-01-01 22:31:03 +02:00
Henrik Rydgård
ce378b231f Delete CPU.cpp/h , cleanup 2013-12-30 00:11:29 +01:00
Henrik Rydgard
2d8429ac48 Assorted cleanup in the MIPS emulation 2013-12-10 13:15:16 +01:00
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ec05146ffd Improve vfpu disasm for a few instructions. 2013-11-29 10:07:15 -08:00
Henrik Rydgard
55500d4bb6 Reorder VFPU registers in memory so that we can flush and reload them in bulk more often. 
Doesn't actually do that yet, that's for the NEON branch.
 2013-11-28 13:27:51 +01:00
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e3834d5833 Avoid some unlikely uninitialized values. 2013-10-26 18:31:14 -07:00
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109ad17ac6 Use a typesafe struct for opcodes. 
Also, correctly read delayslots using Read_Instruction on ARM.
 2013-08-24 15:36:24 -07:00
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46c5a48a86 Clean up some minor aliasing. 2013-08-22 23:31:49 -07:00
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b733bc1a2a Clean up some indents, add some reporting. 2013-05-18 02:09:32 -07:00
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e16514b50d Avoid float copy in vfpu to workaround 32-bit bug. 
This appears to be an MSVC bug (or just precision issue) when using
fast math, only on 32-bit builds.  Anyway, memcpy or u32 * fixes it.

Unfortunately, matrix ops have similar issues and memcpy doesn't seem
to help there.
 2013-05-18 02:09:32 -07:00
Henrik Rydgard
516ca8a0c4 Merge branch 'master' into armjit-fpu 
Conflicts:
	Core/MIPS/ARM/ArmJit.h
	Core/MIPS/x86/CompVFPU.cpp
	GPU/GLES/Framebuffer.cpp
 2013-02-28 23:56:28 +01:00
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01f3c4ecde Log an error if we hit a 1x1 matrix. 2013-02-19 07:46:29 -08:00
Henrik Rydgard
e32721c72a Merge branch 'master' into armjit-fpu 
Conflicts:
	Core/MIPS/MIPSVFPUUtils.cpp
	Core/MIPS/x86/CompVFPU.cpp
	GPU/GLES/VertexDecoder.cpp
 2013-02-19 00:50:33 +01:00
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179fccaff7 Tests say matrices apply mask to last col (kinda.) 
It seems inconsistent but probably better than before.  Also add an error.
 2013-02-18 13:19:16 -08:00
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be631dea64 Disasm transposed vectors properly. 2013-02-17 17:52:58 -08:00
Henrik Rydgard
159f423135 VFPUutil style & simplification 2013-02-16 09:28:56 +01:00
Henrik Rydgard
909b768f47 Don't need separate variables for writemask. Some optimizations. 2013-02-16 09:28:55 +01:00
Henrik Rydgard
526335cacf VFPUutil style & simplification 2013-02-15 23:09:02 +01:00
Henrik Rydgard
d22e258943 Don't need separate variables for writemask. Some optimizations. 2013-02-15 22:56:38 +01:00
Henrik Rydgard
aabc0aa9ef Quick implementation of LV.Q and SV.Q in x86/x64 JIT 2013-01-25 19:50:30 +01:00
Henrik Rydgard
64cc573703 Switch to "GPL 2.0 or later" for various reasons. I wrote most of the code I imported from Dolphin (which is GPL2-but-not-later), so it should be OK. 2012-11-04 23:24:00 +01:00
Henrik Rydgard
4f7ad15758 Add snapshot of the whole source code. 2012-11-01 16:19:01 +01:00