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2303 commits

Author SHA1 Message Date
Henrik Rydgård
250ea5e592
Merge pull request #16407 from unknownbrackets/jit-wx 
In jits, protect and unprotect using better estimates
 2022-11-20 20:39:04 +01:00
Unknown W. Brackets
b2798c7ada jit: Add more reasonable estimates for RX protect. 2022-11-20 10:55:35 -08:00
Henrik Rydgård
15e66080df
Merge pull request #16396 from unknownbrackets/ir-vneg 
Correct misbehavior on uninitialized values in IR
 2022-11-19 06:59:29 +01:00
Unknown W. Brackets
c085413326 irjit: Consistently check vec4 safety. 
Just to prevent confusion/surprises, this is clearer.
 2022-11-18 19:06:50 -08:00
Unknown W. Brackets
ada0674415 irjit: Allow VV2Op SIMD with exact overlap. 
None of these look at other lanes.
 2022-11-18 17:54:58 -08:00
Unknown W. Brackets
2419e5680a irjit: Correct VV2Op SIMD check. 
It's unlikely, but possible, uninitialized data could cause
IsConsecutive4() to return true when n < 4.
 2022-11-18 17:53:53 -08:00
Unknown W. Brackets
0f79afa172 interp: Support memory breakpoints too. 2022-11-13 17:45:43 -08:00
Unknown W. Brackets
f9da9e6b60 interp: Centralize memory size handling. 2022-11-13 17:38:53 -08:00
Unknown W. Brackets
76cf4dbf12 interp: Allow breakpoints in release mode. 2022-11-13 16:52:40 -08:00
Unknown W. Brackets
1662bd3bb8 interp: Allow resume from breakpoint. 2022-11-13 16:03:29 -08:00
Unknown W. Brackets
46182990cf GPU: Hook US version of Marvel Alliance upload. 
See #9852.  Appears to be the same basic func, but something resulted in a
different hash.  Register use for from/to seems the same.
 2022-11-11 21:51:25 -08:00
Henrik Rydgård
e97d5498c6
Merge pull request #16306 from unknownbrackets/ir-prefixes 
irjit: Correct prefix validation
 2022-10-31 09:11:52 +01:00
Unknown W. Brackets
eef29d5e95 irjit: Correct prefix validation. 
Some vcmps, etc. were perfectly valid but were forcing to interp.
This also catches more cases that should go to interp correctly.
 2022-10-30 23:15:54 -07:00
Unknown W. Brackets
2da1bf7ffc interp: Correct dprefix accuracy for vrot. 
Ignores cosine lane, not always x.
 2022-10-30 21:47:28 -07:00
Unknown W. Brackets
56ff555309 irjit: Fix unordered float compares. 2022-10-30 21:12:59 -07:00
Henrik Rydgård
ba32ef5ea5
Merge pull request #16302 from unknownbrackets/vrot-overlap 
Handle vrot overlap and vscl/vmscl prefixes more accurately
 2022-10-30 07:24:23 +01:00
Unknown W. Brackets
bbdc8a8f98 interp: Correct vscl/vmscl t prefix handling. 
This makes more sense.  Fixes Dissidia 012 issues.
 2022-10-29 22:43:30 -07:00
Unknown W. Brackets
3f997518f3 irjit: Handle vrot overlap more correctly. 
Sine ignores overlap, cosine does not.
 2022-10-29 22:25:25 -07:00
Unknown W. Brackets
17d94cd358 SaveState: Restore replacements in only one place. 2022-10-29 17:59:35 -07:00
Unknown W. Brackets
0a98ac43fa Debugger: Allow currently-invalid memory reference. 2022-10-29 17:43:35 -07:00
Unknown W. Brackets
b9de1a44df jit: Reduce some include pollution. 
Usually no need for all of MIPSAnalyst.
 2022-10-27 23:26:44 -07:00
Unknown W. Brackets
813bfded92
x86jit: Correct vh2f NAN handling (#16275) 
* x86jit: Correct vh2f NAN handling.

Allows another test to pass.

* x86jit: Reuse MAccessibleDisp().
 2022-10-23 10:09:29 +02:00
Henrik Rydgård
0719f1d4ea Merge branch 'cheat-icache' (PR #16234) 2022-10-16 09:55:30 +02:00
Unknown W. Brackets
0226d95000 jit: Run invalidates immediately. 
Previously, I thought we might clear native code when invalidating - we
don't.  We only do that when clearing.
 2022-10-15 18:52:46 -07:00
Unknown W. Brackets
fa5f9d5e74 jit: Consistently check range on invalidate. 
We did this on x86, we should do it everywhere or nowhere.
 2022-10-15 18:30:13 -07:00
Unknown W. Brackets
c4bf2cb5c0 jit: Ignore zero byte icache invalidates. 
These were getting marked pending and were clearing all cache, causing
performance concerns in for example LittleBigPlanet.
 2022-10-15 18:27:52 -07:00
Henrik Rydgård
26f6afbfa7 Followup to #16205, fix one more instance of the problem. 2022-10-12 01:02:54 +02:00
Henrik Rydgård
df5b51990d ArmJit: Save/restore downcount where needed, we missed a few cases. 2022-10-11 15:50:37 +02:00
Henrik Rydgård
a34e32abe1 Revert "Disables "ForceCheck" on jit invalidation on ARM32, introduced in #16194" 
This reverts commit bc28f54612.
 2022-10-11 15:42:59 +02:00
Henrik Rydgård
bc28f54612 Disables "ForceCheck" on jit invalidation on ARM32, introduced in #16194 
I'm not sure if we should call it at all here, but at least this makes
games work again on ARM32. Will need more investigation.
 2022-10-11 10:10:52 +02:00
Unknown W. Brackets
728748b108 MIPS: Fix non standard layout offsets. 2022-10-10 17:30:15 -07:00
Unknown W. Brackets
825450a373 jit: Defer invalidations made while running. 
Previously, invalidating icache could happen while running, which might
cause the CPU to return into outer space.  This runs such invalidations
after letting the CPU exit.

It was easy to trigger this with the debugger: step using the GE debugger,
add a CPU memory breakpoint, then resume from the GE debugger.
However, cheats and the like could cause similar issues.
 2022-10-09 21:26:13 -07:00
Unknown W. Brackets
057661380e GPU: Hook Gods Eater Burst avatar read. 
Currently not working since depth comes back as 0.
 2022-10-09 00:52:35 -07:00
Herman Semenov
29b87e0c0b
Merge branch 'master' into master 2022-10-03 07:49:13 +00:00
Unknown W. Brackets
ac335ad61a armips: Update to UTF-8/c++17 armips. 2022-09-30 19:48:14 -07:00
Unknown W. Brackets
c49b91c62b armips: Update to latest. 2022-09-30 17:47:43 -07:00
lainon
3cdf72b68b Better readability and optimization insertion into container by replacing 'insert' -> 'emplace', 'push_back' -> 'emplace_back' 2022-09-30 12:35:28 +03:00
lainon
b304551747 Code readability, vec reserve() and remove excess c_str() 2022-09-30 12:31:32 +03:00
lainon
fec708489a Correct cleaning string and remove unused vars 2022-09-30 12:26:30 +03:00
Unknown W. Brackets
f75dadd1d6 arm64jit: Handle branch/jump in branch delay slots. 2022-09-03 21:04:54 -07:00
Unknown W. Brackets
bac36df453 x86jit: Refactor and fix jump in branch delay slot. 
This seems cleaner, instead of the duplication of lines for each branch
type.
 2022-09-03 19:58:46 -07:00
Unknown W. Brackets
d08ee44cf4 irjit: Handle branch/jump in branch delay slots. 
See #15952 for more detail.
 2022-09-03 19:05:31 -07:00
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0fc3619d1d interp: Handle jumps in branch delay slots better. 
This matches tests from a PSP-2000.  Seems to consistently run the
instruction even if likely, which writes rd.

If the likely branch is not taken, the jump in the delay slot is taken.
However, it should cancel the rd write (not implemented here.)
 2022-09-03 13:15:21 -07:00
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8e7847f6d9 UI: Show return address for exec crashes. 2022-08-21 14:49:34 -07:00
Unknown W. Brackets
80e481bbdc Core: Show exception on misaligned jump. 2022-08-21 14:49:34 -07:00
Unknown W. Brackets
90517ace59 irjit: Validate alignment in slow memory mode. 2022-08-21 13:24:10 -07:00
Unknown W. Brackets
6715f41410 irjit: Add constructs for validing mem access. 
Basically to allow slow/fast memory to work with IR, including for
alignment checks.
 2022-08-21 13:01:23 -07:00
Unknown W. Brackets
7b081a61c8 irjit: Correct another PurgeTemps case. 
In this case:
  Mov A, B
  AndConst A, A, 1
  Load32 C, A, 0

Was still swapping the Load32 to B, not just the AndConst.

Fixes #15735.
 2022-07-27 19:38:16 -07:00
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5abf1362a2 irjit: Clarify PurgeTemps, guard a couple ops. 
Although I think we skip simplify passes on breakpoints entirely, safer to
exclude these ops.
 2022-07-27 19:36:53 -07:00
Unknown W. Brackets
2154f747fc irjit: Simplify more arithmetic to Movs. 
Later passes rely on things being Mov, so better to have them more often.
 2022-07-24 11:35:54 -07:00