11 commits

Author	SHA1	Message	Date
Unknown W. Brackets	89c18d8077	riscv: Cleanup missing Poison, Crash.	2023-02-12 12:10:29 -08:00
Unknown W. Brackets	b2798c7ada	jit: Add more reasonable estimates for RX protect.	2022-11-20 10:55:35 -08:00
Henrik Rydgård	cd92151de7	Add ARM64_NEON compile arch flag ... This allows doing ARM64 builds without NEON support, and allows simplifying some checks.	2022-06-25 07:29:20 +02:00
Unknown W. Brackets	6ec819878a	samplerjit: Reduce prolog/epilog spill. ... Track reg usage so we only push/pop what we need.	2022-01-19 00:03:59 -08:00
Unknown W. Brackets	357e2e9d68	softjit: Simplify constant writes.	2022-01-19 00:03:59 -08:00
Unknown W. Brackets	c2985bca31	softjit: Centralize some common funcs from sampler. ... No need to duplicate this code.	2022-01-19 00:03:59 -08:00
Unknown W. Brackets	d7c25b3e7c	samplerjit: Refactor nearest using reg cache.	2021-12-04 13:04:53 -08:00
Unknown W. Brackets	4aa5bee14c	softjit: Make it an error to unlock a temp. ... Also fix some register usage in logic ops.	2021-12-01 21:50:02 -08:00
Unknown W. Brackets	1c5615624a	softjit: Oops, correct allocation typo. ... Decided to leave these for paired operations.	2021-12-01 21:37:55 -08:00
Unknown W. Brackets	99c213f244	softjit: Centralize argument register allocation.	2021-11-28 15:53:24 -08:00
Unknown W. Brackets	3d5bced296	softjit: Rename reg cache so it can be reused. ... Intentionally just the name changes in this commit.	2021-11-28 08:03:15 -08:00