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2326 commits

Author SHA1 Message Date
Henrik Rydgård
718cb9ee4a Reorder savestates to put memory before CoreTiming. 
Also, don't clear the JIT for rounding after saving, only after loading.
 2023-02-14 16:43:22 +01:00
Unknown W. Brackets
89c18d8077 riscv: Cleanup missing Poison, Crash. 2023-02-12 12:10:29 -08:00
Henrik Rydgård
9e736ca50c Workaround for sin/cos issue in GTA on Mac (and maybe others) 2023-02-07 17:43:12 +01:00
Henrik Rydgård
6dc930feb7
Merge pull request #16796 from unknownbrackets/icache-typo 
jit: Fix reporting of icache invalidate near PC
 2023-01-12 07:30:24 +01:00
Unknown W. Brackets
8341b09087 jit: Fix reporting of icache invalidate near PC. 
Reversed the check, that's what I get for not testing it.
 2023-01-11 20:22:09 -08:00
Henrik Rydgård
e1a48d74c4 A bit more GetPointer cleanup. 
Probably not worth it for performance reasons, but some semantic cleanup
is good, especially the accidental GetPointer -> writable casts without
using GetPointerWrite.

Using Unchecked on already checked pointers, or when we'd crash anyway
if it returned nullptr, is good for clarity.
 2023-01-10 12:13:47 +01:00
Unknown W. Brackets
dea9cac16c Core: Add range checks to some helpers and similar. 2023-01-09 16:56:18 -08:00
Unknown W. Brackets
1f66c1d689 jit: Also report invalidation near PC. 2023-01-06 19:51:43 -08:00
Unknown W. Brackets
b073d3e207 jit: Report unaligned icache invalidations. 
And over invalidate them a bit.
 2023-01-06 19:46:43 -08:00
Unknown W. Brackets
fb13dbf169 riscv: Correct type warning, oops. 2023-01-04 21:42:22 -08:00
Henrik Rydgård
14bd411036 Round addr to nearest cacheline when invalidating 2023-01-04 11:40:53 +01:00
Henrik Rydgård
830f1064e6
Merge pull request #16676 from unknownbrackets/riscv-disasm 
Add disassembler for RISC-V
 2023-01-04 09:52:56 +01:00
Henrik Rydgård
700a018ef0 IRInterpreter: Use alignment as access size in exceptions 2023-01-01 20:48:16 +01:00
Henrik Rydgård
aa80659530 Memory exception: Add facility to track size 
Might theoretically help in tracking some things down.

Not fully utilized yet, the fault handler needs to extract the
information from the faulting instruction. But we can use it for
GetPointerRange etc.
 2023-01-01 20:30:29 +01:00
Unknown W. Brackets
cee8bfd5cf riscv: Avoid a jit warning. 
We'll end up doing the same as arm64, most likely.
 2023-01-01 10:28:54 -08:00
Unknown W. Brackets
77849d3eed riscv: Add disassembler. 
From https://github.com/anthony-coulter/riscv-disassembler.
Modified slightly to pull in less headers in the h, prefix funcs.
 2023-01-01 10:28:53 -08:00
Unknown W. Brackets
808f47fd15 Core: Prevent crash if FakeJit is actually used. 
Just make it fall back to the interpreter.
 2022-12-24 17:42:50 +00:00
Unknown W. Brackets
b9fe48f42d Crash: Lookup block numbers more efficiently. 
We only care about the first one in these places anyway.  Also make sure
we don't try to match an invalid block number.
 2022-12-20 21:02:52 -08:00
Unknown W. Brackets
21332c677b Build: Allow compiling without armips. 2022-12-17 10:08:46 -08:00
Henrik Rydgård
e48a1599d4 Delete a few obsolete lines of code 2022-12-11 10:01:55 +01:00
Unknown W. Brackets
9cfcbc46e6 Global: Cleanup initialization/pointer checks. 
Cleaning up a lot of cases of uninitialized data, unchecked return values
for failures, and similar.
 2022-12-10 21:13:36 -08:00
Unknown W. Brackets
a7b7bf7826 Global: Set many read-only params as const. 
This makes what they do and which args to use clearer, if nothing else.
 2022-12-10 21:13:36 -08:00
Unknown W. Brackets
f44852bb18 Global: Cleanup virtual/override specifiers. 
Also missing virtual destructors, hidden non-overrides, etc.
 2022-12-10 21:13:36 -08:00
Henrik Rydgård
250ea5e592
Merge pull request #16407 from unknownbrackets/jit-wx 
In jits, protect and unprotect using better estimates
 2022-11-20 20:39:04 +01:00
Unknown W. Brackets
b2798c7ada jit: Add more reasonable estimates for RX protect. 2022-11-20 10:55:35 -08:00
Henrik Rydgård
15e66080df
Merge pull request #16396 from unknownbrackets/ir-vneg 
Correct misbehavior on uninitialized values in IR
 2022-11-19 06:59:29 +01:00
Unknown W. Brackets
c085413326 irjit: Consistently check vec4 safety. 
Just to prevent confusion/surprises, this is clearer.
 2022-11-18 19:06:50 -08:00
Unknown W. Brackets
ada0674415 irjit: Allow VV2Op SIMD with exact overlap. 
None of these look at other lanes.
 2022-11-18 17:54:58 -08:00
Unknown W. Brackets
2419e5680a irjit: Correct VV2Op SIMD check. 
It's unlikely, but possible, uninitialized data could cause
IsConsecutive4() to return true when n < 4.
 2022-11-18 17:53:53 -08:00
Unknown W. Brackets
0f79afa172 interp: Support memory breakpoints too. 2022-11-13 17:45:43 -08:00
Unknown W. Brackets
f9da9e6b60 interp: Centralize memory size handling. 2022-11-13 17:38:53 -08:00
Unknown W. Brackets
76cf4dbf12 interp: Allow breakpoints in release mode. 2022-11-13 16:52:40 -08:00
Unknown W. Brackets
1662bd3bb8 interp: Allow resume from breakpoint. 2022-11-13 16:03:29 -08:00
Unknown W. Brackets
46182990cf GPU: Hook US version of Marvel Alliance upload. 
See #9852.  Appears to be the same basic func, but something resulted in a
different hash.  Register use for from/to seems the same.
 2022-11-11 21:51:25 -08:00
Henrik Rydgård
e97d5498c6
Merge pull request #16306 from unknownbrackets/ir-prefixes 
irjit: Correct prefix validation
 2022-10-31 09:11:52 +01:00
Unknown W. Brackets
eef29d5e95 irjit: Correct prefix validation. 
Some vcmps, etc. were perfectly valid but were forcing to interp.
This also catches more cases that should go to interp correctly.
 2022-10-30 23:15:54 -07:00
Unknown W. Brackets
2da1bf7ffc interp: Correct dprefix accuracy for vrot. 
Ignores cosine lane, not always x.
 2022-10-30 21:47:28 -07:00
Unknown W. Brackets
56ff555309 irjit: Fix unordered float compares. 2022-10-30 21:12:59 -07:00
Henrik Rydgård
ba32ef5ea5
Merge pull request #16302 from unknownbrackets/vrot-overlap 
Handle vrot overlap and vscl/vmscl prefixes more accurately
 2022-10-30 07:24:23 +01:00
Unknown W. Brackets
bbdc8a8f98 interp: Correct vscl/vmscl t prefix handling. 
This makes more sense.  Fixes Dissidia 012 issues.
 2022-10-29 22:43:30 -07:00
Unknown W. Brackets
3f997518f3 irjit: Handle vrot overlap more correctly. 
Sine ignores overlap, cosine does not.
 2022-10-29 22:25:25 -07:00
Unknown W. Brackets
17d94cd358 SaveState: Restore replacements in only one place. 2022-10-29 17:59:35 -07:00
Unknown W. Brackets
0a98ac43fa Debugger: Allow currently-invalid memory reference. 2022-10-29 17:43:35 -07:00
Unknown W. Brackets
b9de1a44df jit: Reduce some include pollution. 
Usually no need for all of MIPSAnalyst.
 2022-10-27 23:26:44 -07:00
Unknown W. Brackets
813bfded92
x86jit: Correct vh2f NAN handling (#16275) 
* x86jit: Correct vh2f NAN handling.

Allows another test to pass.

* x86jit: Reuse MAccessibleDisp().
 2022-10-23 10:09:29 +02:00
Henrik Rydgård
0719f1d4ea Merge branch 'cheat-icache' (PR #16234) 2022-10-16 09:55:30 +02:00
Unknown W. Brackets
0226d95000 jit: Run invalidates immediately. 
Previously, I thought we might clear native code when invalidating - we
don't.  We only do that when clearing.
 2022-10-15 18:52:46 -07:00
Unknown W. Brackets
fa5f9d5e74 jit: Consistently check range on invalidate. 
We did this on x86, we should do it everywhere or nowhere.
 2022-10-15 18:30:13 -07:00
Unknown W. Brackets
c4bf2cb5c0 jit: Ignore zero byte icache invalidates. 
These were getting marked pending and were clearing all cache, causing
performance concerns in for example LittleBigPlanet.
 2022-10-15 18:27:52 -07:00
Henrik Rydgård
26f6afbfa7 Followup to #16205, fix one more instance of the problem. 2022-10-12 01:02:54 +02:00