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61 commits

Author SHA1 Message Date
Unknown W. Brackets
cd46f0b4cb irjit: Cache IR metadata lookups. 
This improves compilation performance, because all those lookups were
adding up.
 2023-09-30 15:56:53 -07:00
Unknown W. Brackets
1a37b4b3fd Core: Stop including Rng so widely. 
It's no longer on the MIPS struct.
 2023-09-07 17:56:46 -07:00
Unknown W. Brackets
c85886c11e irjit: Use enum for rounding modes. 2023-09-01 22:29:24 -07:00
Henrik Rydgård
24e0cb013b
Merge pull request #17991 from unknownbrackets/x86-jit-dot 
x86jit: Improve vdot performance
 2023-08-28 10:15:03 +02:00
Unknown W. Brackets
35fe15d718 x86jit: Do not use Vec4Dot for vdot.t. 
It was much slower to do so in LittleBigPlanet.
 2023-08-27 12:39:21 -07:00
Unknown W. Brackets
f263698897 irjit: Cleanup temp purging on exit. 
We were sometimes considering it read by exit and not purging.
 2023-08-27 12:26:05 -07:00
Unknown W. Brackets
57123e8f9e irjit: Reserve some arrays that churn. 
Improves IR compile time by around 20-30%.
 2023-08-20 08:59:47 -07:00
Unknown W. Brackets
bd1d93ae6f irjit: Cleanup Write() calls with extra const. 
Some instructions, such as Vec4Blend, are encoded requiring the const
field, and this interface was designed when we used a pool.
 2023-08-19 16:23:42 -07:00
Unknown W. Brackets
159b41a0fa irjit: Fuse unaligned svl.q/svr.q together. 
They're almost never used outside paired, which we can do on most
platforms easily.
 2023-08-13 18:10:40 -07:00
Unknown W. Brackets
2e6dbab5fa irjit: Add flag to prefer Vec4, use for add/sub. 
This will improve things when using SIMD.
 2023-08-13 18:10:40 -07:00
Unknown W. Brackets
2b36e0a625 irjit: ZeroFpCond -> FpCondFromReg. 
We already have a zero reg, so this is more useful and symmetrical.
 2023-08-13 10:40:47 -07:00
Unknown W. Brackets
79ca880ac7 irjit: Implement vqmul, add Vec4Blend. 
Should be useful more places.
 2023-08-06 13:38:00 -07:00
Unknown W. Brackets
c24e3ef831 riscv: Implement ll/sc. 2023-07-30 00:45:51 -07:00
Henrik Rydgård
180bda6f6b
Merge pull request #17799 from unknownbrackets/irjit-lsu 
Add ll/sc to IR and x86jit
 2023-07-30 09:15:55 +02:00
Unknown W. Brackets
e228748449 irjit: Add FCvtScaledSW to safely scale vi2f. 2023-07-29 18:30:15 -07:00
Unknown W. Brackets
a5a2671af3 irjit: Implement vf2ix. 
Used in LittleBigPlanet when playing intro movies.
 2023-07-29 18:01:08 -07:00
Unknown W. Brackets
df2462b1d9 irjit: Implement ll/sc. 
These occur more than I expected in LittleBigPlanet while loading.
 2023-07-29 17:57:44 -07:00
Unknown W. Brackets
9157d992ac jit-ir: Implement cfc1/ctc1. 
This makes it so we can track rounding mode changes.
 2023-07-25 20:33:56 -07:00
Unknown W. Brackets
b2d3c750f1 irjit: Define a specific IRReg type. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets
6715f41410 irjit: Add constructs for validing mem access. 
Basically to allow slow/fast memory to work with IR, including for
alignment checks.
 2022-08-21 13:01:23 -07:00
Unknown W. Brackets
cae0815095 jit: Avoid using mips identifier directly. 
Apparently this gets defined on mips systems.
 2021-02-26 07:24:58 -08:00
Unknown W. Brackets
46649a218e Core: Add flags to disable jit features. 
Not actually disabling yet, just setup.
 2019-02-03 13:58:24 -08:00
Unknown W. Brackets
6dda053365 irjit: Add dedicated ops for lwl/swl and friends. 
Temporarily removes optimizations.
 2018-01-07 21:05:57 -08:00
Henrik Rydgård
331a8f91e8 Fix that weird unordered compare mode, hopefully 2018-01-04 20:06:26 +01:00
Unknown W. Brackets
cffb2d61a7 irjit: Embed constant inside IRInst. 
This simplifies a bunch of code and improves compile performance by about
30%, at the cost of a bit more memory.
 2018-01-03 23:24:04 -08:00
Henrik Rydgård
3ac2350ad6 IR Interpreter: Add a comment, minor cleanup, minor SSE stuff. 2018-01-03 16:31:55 +01:00
Unknown W. Brackets
b37ba9e599 irjit: Add options for compile/optimize steps. 
This way the backend can set flags for the type of IR it wants.  It's
seems too complex to combine certain things like lwl/lwr in a pass.
 2018-01-01 08:38:12 -08:00
Unknown W. Brackets
671be24105 irjit: Add extra temps to make lwl/swl/etc. easier. 2018-01-01 08:38:11 -08:00
Florent Castelli
4145b60a0e symbian: Remove! 2016-10-11 18:49:08 +02:00
Unknown W. Brackets
4578c3cb54 jit-ir: Implement memory breakpoints. 
These generally work, but likely delay slots will make downcount slightly
off, and won't resume when you hit run again without manually stepping
through them.
 2016-07-02 16:38:30 -07:00
Unknown W. Brackets
6fb34d0bee jit-ir: Add initial breakpoint support. 
No memory breakpoints yet, and cache isn't cleared yet so these don't work
exactly the way you might expect...
 2016-07-01 17:15:57 -07:00
Henrik Rydgard
d6c2b6e9ae Most of vi2x 2016-05-15 11:46:01 +02:00
Henrik Rydgard
905af75925 vx2i, vbfy, vsgn 2016-05-15 10:57:43 +02:00
Unknown W. Brackets
4ac773e8b4 jit-ir: Implement bit reverse instruction. 2016-05-14 18:21:42 -07:00
Henrik Rydgard
64eda6a4ec IR: Split Syscall into Syscall and ExitToPC, so we can put ApplyRoundingMode in between. 2016-05-14 14:32:22 +02:00
Unknown W. Brackets
efc8a8e353 Hack to make Symbian build. 2016-05-13 23:56:17 -07:00
Henrik Rydgard
5b2504120d Optimize some common prefixes 2016-05-13 20:15:20 +02:00
Henrik Rydgard
f636b2a315 Minor build and other fixes 2016-05-13 19:31:27 +02:00
Unknown W. Brackets
d06c6c080c jit-ir: Expand unused regs to regular GPRs. 2016-05-12 18:30:55 -07:00
Unknown W. Brackets
99468c6fc1 jit-ir: Optimize out unused temp regs. 
This way, if constants have made the temp obsolete (common with ins, for
example), it won't even get set anymore.
 2016-05-12 18:30:53 -07:00
Henrik Rydgard
7268abec61 IR: vcmp, vcmov, vhdp 2016-05-12 22:35:31 +02:00
Henrik Rydgard
850d0abc91 IR: More VFPU. Support normal fp compares. 2016-05-12 20:16:15 +02:00
Henrik Rydgard
2cbfb192c4 IR: Lots more VFPU support, some with SIMD 2016-05-12 12:17:25 +02:00
Henrik Rydgard
219548b8e2 Prefix prep 2016-05-11 00:16:07 +02:00
Henrik Rydgard
b3dd36982f Prefix prep 2016-05-10 23:14:26 +02:00
Henrik Rydgard
db1d1ff9fd IR: Merge the FPU and VFPU instruction sets, no reason to keep them apart 2016-05-10 22:55:27 +02:00
Henrik Rydgard
45efcda6b1 IR: Some more VFPU 2016-05-10 21:50:08 +02:00
Henrik Rydgard
558bb197c7 More VFPU 2016-05-09 23:47:56 +02:00
Unknown W. Brackets
f6d245f3c4 jit-ir: Remove redundant simplify pass. 
This is just doing the same thing as the const folding pass, really.
 2016-05-09 00:13:01 -07:00
Unknown W. Brackets
6bd31ecb27 jit-ir: Flush consts better for a few f/v ops. 2016-05-08 21:37:46 -07:00