11 commits

Author	SHA1	Message	Date
Unknown W. Brackets	067a033dc0	riscv: Add FPU regcache.	2023-07-25 20:33:56 -07:00
Unknown W. Brackets	b9de1a44df	jit: Reduce some include pollution. ... Usually no need for all of MIPSAnalyst.	2022-10-27 23:26:44 -07:00
Unknown W. Brackets	cae0815095	jit: Avoid using mips identifier directly. ... Apparently this gets defined on mips systems.	2021-02-26 07:24:58 -08:00
Florent Castelli	373db56a16	blackberry: Remove!	2016-10-11 17:40:32 +02:00
Henrik Rydgard	9fe382ad18	ARM64: Shortcut moves between gpr and vfpu when not mapped	2015-07-11 23:53:06 +02:00
Henrik Rydgard	1575025b3d	ARM64: Store back fp registers in pairs where possible	2015-07-11 13:52:46 +02:00
Henrik Rydgård	d014d420db	Unify JitOptions across the backends. ... This is required to make ExtractIR not a member of the various backends.	2015-04-12 11:41:26 -07:00
Henrik Rydgard	1b1ab73b0f	ARM64: Enable some more VFPU instructions, some code cleanup	2015-04-06 18:13:29 +02:00
Henrik Rydgard	8df8c210d1	ARM64: Start porting over VFPU stuff from ARM, fix regalloc bug	2015-04-06 18:13:28 +02:00
Henrik Rydgard	d2c746dd64	ARM64: Get the FP reg cache working, implement some basic FP arith	2015-04-06 18:13:11 +02:00
Henrik Rydgard	b309c83973	Initial work on ARM64, based on the ARM jit.	2015-04-06 18:13:01 +02:00