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Fix the vrndi.s output range.

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Was previously outputting only valid positive float values, but should use
a much wider range of a u32.

Might've affected randomness in some games.
This commit is contained in:
Unknown W. Brackets 2014-09-01 22:33:01 -07:00
parent baf465500a
commit fd1b01b573
1 changed files with 14 additions and 23 deletions
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37
Core/MIPS/MIPSIntVFPU.cpp
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@ -70,6 +70,12 @@
#define M_SQRT1_2 0.707106781186547524401f #define M_SQRT1_2 0.707106781186547524401f
#endif #endif
union FloatBits {
float f[4];
u32 u[4];
int i[4];
};
// Preserves NaN in first param, takes sign of equal second param. // Preserves NaN in first param, takes sign of equal second param.
// Technically, std::max may do this but it's undefined. // Technically, std::max may do this but it's undefined.
inline float nanmax(float f, float cst) inline float nanmax(float f, float cst)
@ -1177,7 +1183,8 @@ namespace MIPSInt
ReadVector(s, sz, vs); ReadVector(s, sz, vs);
ApplySwizzleS(s, sz); ApplySwizzleS(s, sz);
ReadVector(t, sz, vt); ReadVector(t, sz, vt);
// TODO: Does t have swizzle? // TODO: The swizzle on t behaves oddly with constants, but sign changes seem to work.
// Also, seems to round in a non-standard way (sometimes toward zero, not always.)
d[0] = s[0] * t[1] - s[1] * t[0]; d[0] = s[0] * t[1] - s[1] * t[0];
ApplyPrefixD(d, sz); ApplyPrefixD(d, sz);
WriteVector(d, V_Single, vd); WriteVector(d, V_Single, vd);
@ -1267,7 +1274,7 @@ namespace MIPSInt
void Int_VrndX(MIPSOpcode op) void Int_VrndX(MIPSOpcode op)
{ {
float d[4]; FloatBits d;
int vd = _VD; int vd = _VD;
VectorSize sz = GetVecSize(op); VectorSize sz = GetVecSize(op);
int n = GetNumVectorElements(sz); int n = GetNumVectorElements(sz);
@ -1275,14 +1282,14 @@ namespace MIPSInt
{ {
switch ((op >> 16) & 0x1f) switch ((op >> 16) & 0x1f)
{ {
case 1: d[i] = (float)currentMIPS->rng.R32(); break; // vrndi - TODO: copy bits instead? case 1: d.u[i] = currentMIPS->rng.R32(); break; // vrndi
case 2: d[i] = 1.0f + ((float)currentMIPS->rng.R32() / 0xFFFFFFFF); break; // vrndf1 TODO: make more accurate case 2: d.f[i] = 1.0f + ((float)currentMIPS->rng.R32() / 0xFFFFFFFF); break; // vrndf1 TODO: make more accurate
case 3: d[i] = 2.0f + 2 * ((float)currentMIPS->rng.R32() / 0xFFFFFFFF); break; // vrndf2 TODO: make more accurate case 3: d.f[i] = 2.0f + 2 * ((float)currentMIPS->rng.R32() / 0xFFFFFFFF); break; // vrndf2 TODO: make more accurate
default: _dbg_assert_msg_(CPU,0,"Trying to interpret instruction that can't be interpreted"); default: _dbg_assert_msg_(CPU,0,"Trying to interpret instruction that can't be interpreted");
} }
} }
ApplyPrefixD(d, sz); ApplyPrefixD(d.f, sz);
WriteVector(d, sz, vd); WriteVector(d.f, sz, vd);
PC += 4; PC += 4;
EatPrefixes(); EatPrefixes();
} }
@ -1531,12 +1538,6 @@ namespace MIPSInt
VectorSize sz = GetVecSize(op); VectorSize sz = GetVecSize(op);
int numElements = GetNumVectorElements(sz); int numElements = GetNumVectorElements(sz);
union FloatBits {
float f[4];
u32 u[4];
int i[4];
};
FloatBits s; FloatBits s;
FloatBits t; FloatBits t;
FloatBits d; FloatBits d;
@ -1810,11 +1811,6 @@ bad:
int vs = _VS; int vs = _VS;
VectorSize sz = GetVecSize(op); VectorSize sz = GetVecSize(op);
union FloatBits {
float f[4];
u32 u[4];
};
FloatBits d; FloatBits d;
FloatBits s; FloatBits s;
u8 exp = (u8)((op >> 16) & 0xFF); u8 exp = (u8)((op >> 16) & 0xFF);
@ -1856,11 +1852,6 @@ bad:
int vt = _VT; int vt = _VT;
VectorSize sz = GetVecSize(op); VectorSize sz = GetVecSize(op);
union FloatBits {
float f[4];
u32 u[4];
};
FloatBits d; FloatBits d;
FloatBits s; FloatBits s;
u8 exp = (u8)(127 + VI(vt)); u8 exp = (u8)(127 + VI(vt));