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jit: MAP_NOINIT should always mean MAP_DIRTY.

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Unknown W. Brackets 2014-11-29 00:14:08 -08:00
parent 0839ce59e1
commit f6f943de63
9 changed files with 39 additions and 39 deletions
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4
Core/MIPS/ARM/ArmCompLoadStore.cpp
View file

@ -309,7 +309,7 @@ namespace MIPSComp
if (!gpr.IsImm(rs) && rs != rt && (offset <= offsetRange) && offset >= -offsetRange) { if (!gpr.IsImm(rs) && rs != rt && (offset <= offsetRange) && offset >= -offsetRange) {
gpr.SpillLock(rs, rt); gpr.SpillLock(rs, rt);
gpr.MapRegAsPointer(rs); gpr.MapRegAsPointer(rs);
gpr.MapReg(rt, load ? (MAP_NOINIT | MAP_DIRTY) : 0); gpr.MapReg(rt, load ? MAP_NOINIT : 0);
switch (o) { switch (o) {
case 35: LDR (gpr.R(rt), gpr.RPtr(rs), Operand2(offset, TYPE_IMM)); break; case 35: LDR (gpr.R(rt), gpr.RPtr(rs), Operand2(offset, TYPE_IMM)); break;
case 37: LDRH (gpr.R(rt), gpr.RPtr(rs), Operand2(offset, TYPE_IMM)); break; case 37: LDRH (gpr.R(rt), gpr.RPtr(rs), Operand2(offset, TYPE_IMM)); break;
@ -338,7 +338,7 @@ namespace MIPSComp
addrReg = gpr.R(rs); addrReg = gpr.R(rs);
} else { } else {
// In this case, only map rt. rs+offset will be in R0. // In this case, only map rt. rs+offset will be in R0.
gpr.MapReg(rt, load ? (MAP_NOINIT | MAP_DIRTY) : 0); gpr.MapReg(rt, load ? MAP_NOINIT : 0);
gpr.SetRegImm(R0, addr); gpr.SetRegImm(R0, addr);
addrReg = R0; addrReg = R0;
} }

16
Core/MIPS/ARM/ArmRegCache.cpp
View file

@ -144,7 +144,7 @@ void ArmRegCache::SetRegImm(ARMReg reg, u32 imm) {
void ArmRegCache::MapRegTo(ARMReg reg, MIPSGPReg mipsReg, int mapFlags) { void ArmRegCache::MapRegTo(ARMReg reg, MIPSGPReg mipsReg, int mapFlags) {
ar[reg].isDirty = (mapFlags & MAP_DIRTY) ? true : false; ar[reg].isDirty = (mapFlags & MAP_DIRTY) ? true : false;
if (!(mapFlags & MAP_NOINIT)) { if ((mapFlags & MAP_NOINIT) != MAP_NOINIT) {
if (mipsReg == MIPS_REG_ZERO) { if (mipsReg == MIPS_REG_ZERO) {
// If we get a request to load the zero register, at least we won't spend // If we get a request to load the zero register, at least we won't spend
// time on a memory access... // time on a memory access...
@ -243,7 +243,7 @@ ARMReg ArmRegCache::MapReg(MIPSGPReg mipsReg, int mapFlags) {
// add or subtract stuff to it. Later we could allow such things but for now // add or subtract stuff to it. Later we could allow such things but for now
// let's just convert back to a register value by reloading from the backing storage. // let's just convert back to a register value by reloading from the backing storage.
ARMReg armReg = mr[mipsReg].reg; ARMReg armReg = mr[mipsReg].reg;
if (!(mapFlags & MAP_NOINIT)) { if ((mapFlags & MAP_NOINIT) != MAP_NOINIT) {
emit_->LDR(armReg, CTXREG, GetMipsRegOffset(mipsReg)); emit_->LDR(armReg, CTXREG, GetMipsRegOffset(mipsReg));
} }
mr[mipsReg].loc = ML_ARMREG; mr[mipsReg].loc = ML_ARMREG;
@ -312,7 +312,7 @@ void ArmRegCache::MapInIn(MIPSGPReg rd, MIPSGPReg rs) {
void ArmRegCache::MapDirtyIn(MIPSGPReg rd, MIPSGPReg rs, bool avoidLoad) { void ArmRegCache::MapDirtyIn(MIPSGPReg rd, MIPSGPReg rs, bool avoidLoad) {
SpillLock(rd, rs); SpillLock(rd, rs);
bool load = !avoidLoad || rd == rs; bool load = !avoidLoad || rd == rs;
MapReg(rd, MAP_DIRTY | (load ? 0 : MAP_NOINIT)); MapReg(rd, load ? MAP_DIRTY : MAP_NOINIT);
MapReg(rs); MapReg(rs);
ReleaseSpillLocks(); ReleaseSpillLocks();
} }
@ -320,7 +320,7 @@ void ArmRegCache::MapDirtyIn(MIPSGPReg rd, MIPSGPReg rs, bool avoidLoad) {
void ArmRegCache::MapDirtyInIn(MIPSGPReg rd, MIPSGPReg rs, MIPSGPReg rt, bool avoidLoad) { void ArmRegCache::MapDirtyInIn(MIPSGPReg rd, MIPSGPReg rs, MIPSGPReg rt, bool avoidLoad) {
SpillLock(rd, rs, rt); SpillLock(rd, rs, rt);
bool load = !avoidLoad || (rd == rs || rd == rt); bool load = !avoidLoad || (rd == rs || rd == rt);
MapReg(rd, MAP_DIRTY | (load ? 0 : MAP_NOINIT)); MapReg(rd, load ? MAP_DIRTY : MAP_NOINIT);
MapReg(rt); MapReg(rt);
MapReg(rs); MapReg(rs);
ReleaseSpillLocks(); ReleaseSpillLocks();
@ -330,8 +330,8 @@ void ArmRegCache::MapDirtyDirtyIn(MIPSGPReg rd1, MIPSGPReg rd2, MIPSGPReg rs, bo
SpillLock(rd1, rd2, rs); SpillLock(rd1, rd2, rs);
bool load1 = !avoidLoad || rd1 == rs; bool load1 = !avoidLoad || rd1 == rs;
bool load2 = !avoidLoad || rd2 == rs; bool load2 = !avoidLoad || rd2 == rs;
MapReg(rd1, MAP_DIRTY | (load1 ? 0 : MAP_NOINIT)); MapReg(rd1, load1 ? MAP_DIRTY : MAP_NOINIT);
MapReg(rd2, MAP_DIRTY | (load2 ? 0 : MAP_NOINIT)); MapReg(rd2, load2 ? MAP_DIRTY : MAP_NOINIT);
MapReg(rs); MapReg(rs);
ReleaseSpillLocks(); ReleaseSpillLocks();
} }
@ -340,8 +340,8 @@ void ArmRegCache::MapDirtyDirtyInIn(MIPSGPReg rd1, MIPSGPReg rd2, MIPSGPReg rs,
SpillLock(rd1, rd2, rs, rt); SpillLock(rd1, rd2, rs, rt);
bool load1 = !avoidLoad || (rd1 == rs || rd1 == rt); bool load1 = !avoidLoad || (rd1 == rs || rd1 == rt);
bool load2 = !avoidLoad || (rd2 == rs || rd2 == rt); bool load2 = !avoidLoad || (rd2 == rs || rd2 == rt);
MapReg(rd1, MAP_DIRTY | (load1 ? 0 : MAP_NOINIT)); MapReg(rd1, load1 ? MAP_DIRTY : MAP_NOINIT);
MapReg(rd2, MAP_DIRTY | (load2 ? 0 : MAP_NOINIT)); MapReg(rd2, load2 ? MAP_DIRTY : MAP_NOINIT);
MapReg(rt); MapReg(rt);
MapReg(rs); MapReg(rs);
ReleaseSpillLocks(); ReleaseSpillLocks();

2
Core/MIPS/ARM/ArmRegCache.h
View file

@ -72,7 +72,7 @@ struct RegMIPS {
// Initing is the default so the flag is reversed. // Initing is the default so the flag is reversed.
enum { enum {
MAP_DIRTY = 1, MAP_DIRTY = 1,
MAP_NOINIT = 2, MAP_NOINIT = 2 | MAP_DIRTY,
}; };
namespace MIPSComp { namespace MIPSComp {

10
Core/MIPS/ARM/ArmRegCacheFPU.cpp
View file

@ -125,7 +125,7 @@ allocate:
if (ar[reg].mipsReg == -1) { if (ar[reg].mipsReg == -1) {
// That means it's free. Grab it, and load the value into it (if requested). // That means it's free. Grab it, and load the value into it (if requested).
ar[reg].isDirty = (mapFlags & MAP_DIRTY) ? true : false; ar[reg].isDirty = (mapFlags & MAP_DIRTY) ? true : false;
if (!(mapFlags & MAP_NOINIT)) { if ((mapFlags & MAP_NOINIT) != MAP_NOINIT) {
if (mr[mipsReg].loc == ML_MEM && mipsReg < TEMP0) { if (mr[mipsReg].loc == ML_MEM && mipsReg < TEMP0) {
emit_->VLDR((ARMReg)(reg + S0), CTXREG, GetMipsRegOffset(mipsReg)); emit_->VLDR((ARMReg)(reg + S0), CTXREG, GetMipsRegOffset(mipsReg));
} }
@ -172,7 +172,7 @@ void ArmRegCacheFPU::MapInIn(MIPSReg rd, MIPSReg rs) {
void ArmRegCacheFPU::MapDirtyIn(MIPSReg rd, MIPSReg rs, bool avoidLoad) { void ArmRegCacheFPU::MapDirtyIn(MIPSReg rd, MIPSReg rs, bool avoidLoad) {
SpillLock(rd, rs); SpillLock(rd, rs);
bool overlap = avoidLoad && rd == rs; bool overlap = avoidLoad && rd == rs;
MapReg(rd, MAP_DIRTY | (overlap ? 0 : MAP_NOINIT)); MapReg(rd, overlap ? MAP_DIRTY : MAP_NOINIT);
MapReg(rs); MapReg(rs);
ReleaseSpillLock(rd); ReleaseSpillLock(rd);
ReleaseSpillLock(rs); ReleaseSpillLock(rs);
@ -181,7 +181,7 @@ void ArmRegCacheFPU::MapDirtyIn(MIPSReg rd, MIPSReg rs, bool avoidLoad) {
void ArmRegCacheFPU::MapDirtyInIn(MIPSReg rd, MIPSReg rs, MIPSReg rt, bool avoidLoad) { void ArmRegCacheFPU::MapDirtyInIn(MIPSReg rd, MIPSReg rs, MIPSReg rt, bool avoidLoad) {
SpillLock(rd, rs, rt); SpillLock(rd, rs, rt);
bool overlap = avoidLoad && (rd == rs || rd == rt); bool overlap = avoidLoad && (rd == rs || rd == rt);
MapReg(rd, MAP_DIRTY | (overlap ? 0 : MAP_NOINIT)); MapReg(rd, overlap ? MAP_DIRTY : MAP_NOINIT);
MapReg(rt); MapReg(rt);
MapReg(rs); MapReg(rs);
ReleaseSpillLock(rd); ReleaseSpillLock(rd);
@ -243,7 +243,7 @@ void ArmRegCacheFPU::MapDirtyInV(int vd, int vs, bool avoidLoad) {
bool overlap = avoidLoad && (vd == vs); bool overlap = avoidLoad && (vd == vs);
SpillLockV(vd); SpillLockV(vd);
SpillLockV(vs); SpillLockV(vs);
MapRegV(vd, MAP_DIRTY | (overlap ? 0 : MAP_NOINIT)); MapRegV(vd, overlap ? MAP_DIRTY : MAP_NOINIT);
MapRegV(vs); MapRegV(vs);
ReleaseSpillLockV(vd); ReleaseSpillLockV(vd);
ReleaseSpillLockV(vs); ReleaseSpillLockV(vs);
@ -254,7 +254,7 @@ void ArmRegCacheFPU::MapDirtyInInV(int vd, int vs, int vt, bool avoidLoad) {
SpillLockV(vd); SpillLockV(vd);
SpillLockV(vs); SpillLockV(vs);
SpillLockV(vt); SpillLockV(vt);
MapRegV(vd, MAP_DIRTY | (overlap ? 0 : MAP_NOINIT)); MapRegV(vd, overlap ? MAP_DIRTY : MAP_NOINIT);
MapRegV(vs); MapRegV(vs);
MapRegV(vt); MapRegV(vt);
ReleaseSpillLockV(vd); ReleaseSpillLockV(vd);

10
Core/MIPS/PPC/PpcRegCache.cpp
View file

@ -104,7 +104,7 @@ allocate:
if (ar[reg].mipsReg == -1) { if (ar[reg].mipsReg == -1) {
// That means it's free. Grab it, and load the value into it (if requested). // That means it's free. Grab it, and load the value into it (if requested).
ar[reg].isDirty = (mapFlags & MAP_DIRTY) ? true : false; ar[reg].isDirty = (mapFlags & MAP_DIRTY) ? true : false;
if (!(mapFlags & MAP_NOINIT)) { if ((mapFlags & MAP_NOINIT) != MAP_NOINIT) {
if (mr[mipsReg].loc == ML_MEM) { if (mr[mipsReg].loc == ML_MEM) {
if (mipsReg != 0) { if (mipsReg != 0) {
emit_->LWZ((PPCReg)reg, CTXREG, GetMipsRegOffset(mipsReg)); emit_->LWZ((PPCReg)reg, CTXREG, GetMipsRegOffset(mipsReg));
@ -158,7 +158,7 @@ void PpcRegCache::MapInIn(MIPSReg rd, MIPSReg rs) {
void PpcRegCache::MapDirtyIn(MIPSReg rd, MIPSReg rs, bool avoidLoad) { void PpcRegCache::MapDirtyIn(MIPSReg rd, MIPSReg rs, bool avoidLoad) {
SpillLock(rd, rs); SpillLock(rd, rs);
bool load = !avoidLoad || rd == rs; bool load = !avoidLoad || rd == rs;
MapReg(rd, MAP_DIRTY | (load ? 0 : MAP_NOINIT)); MapReg(rd, load ? MAP_DIRTY : MAP_NOINIT);
MapReg(rs); MapReg(rs);
ReleaseSpillLocks(); ReleaseSpillLocks();
} }
@ -166,7 +166,7 @@ void PpcRegCache::MapDirtyIn(MIPSReg rd, MIPSReg rs, bool avoidLoad) {
void PpcRegCache::MapDirtyInIn(MIPSReg rd, MIPSReg rs, MIPSReg rt, bool avoidLoad) { void PpcRegCache::MapDirtyInIn(MIPSReg rd, MIPSReg rs, MIPSReg rt, bool avoidLoad) {
SpillLock(rd, rs, rt); SpillLock(rd, rs, rt);
bool load = !avoidLoad || (rd == rs || rd == rt); bool load = !avoidLoad || (rd == rs || rd == rt);
MapReg(rd, MAP_DIRTY | (load ? 0 : MAP_NOINIT)); MapReg(rd, load ? MAP_DIRTY : MAP_NOINIT);
MapReg(rt); MapReg(rt);
MapReg(rs); MapReg(rs);
ReleaseSpillLocks(); ReleaseSpillLocks();
@ -176,8 +176,8 @@ void PpcRegCache::MapDirtyDirtyInIn(MIPSReg rd1, MIPSReg rd2, MIPSReg rs, MIPSRe
SpillLock(rd1, rd2, rs, rt); SpillLock(rd1, rd2, rs, rt);
bool load1 = !avoidLoad || (rd1 == rs || rd1 == rt); bool load1 = !avoidLoad || (rd1 == rs || rd1 == rt);
bool load2 = !avoidLoad || (rd2 == rs || rd2 == rt); bool load2 = !avoidLoad || (rd2 == rs || rd2 == rt);
MapReg(rd1, MAP_DIRTY | (load1 ? 0 : MAP_NOINIT)); MapReg(rd1, load1 ? MAP_DIRTY : MAP_NOINIT);
MapReg(rd2, MAP_DIRTY | (load2 ? 0 : MAP_NOINIT)); MapReg(rd2, load2 ? MAP_DIRTY : MAP_NOINIT);
MapReg(rt); MapReg(rt);
MapReg(rs); MapReg(rs);
ReleaseSpillLocks(); ReleaseSpillLocks();

2
Core/MIPS/PPC/PpcRegCache.h
View file

@ -92,7 +92,7 @@ struct RegMIPS {
// Initing is the default so the flag is reversed. // Initing is the default so the flag is reversed.
enum { enum {
MAP_DIRTY = 1, MAP_DIRTY = 1,
MAP_NOINIT = 2, MAP_NOINIT = 2 | MAP_DIRTY,
}; };
namespace MIPSComp { namespace MIPSComp {

18
Core/MIPS/x86/CompVFPU.cpp
View file

@ -1063,7 +1063,7 @@ void Jit::Comp_VecDo3(MIPSOpcode op) {
} }
else else
{ {
fpr.MapRegV(dregs[i], (dregs[i] == sregs[i] ? 0 : MAP_NOINIT) | MAP_DIRTY); fpr.MapRegV(dregs[i], dregs[i] == sregs[i] ? MAP_DIRTY : MAP_NOINIT);
fpr.SpillLockV(dregs[i]); fpr.SpillLockV(dregs[i]);
tempxregs[i] = fpr.VX(dregs[i]); tempxregs[i] = fpr.VX(dregs[i]);
} }
@ -1415,7 +1415,7 @@ void Jit::Comp_Vi2f(MIPSOpcode op) {
if (*mult != 1.0f) if (*mult != 1.0f)
MOVSS(XMM1, M(mult)); MOVSS(XMM1, M(mult));
for (int i = 0; i < n; i++) { for (int i = 0; i < n; i++) {
fpr.MapRegV(tempregs[i], (sregs[i] == dregs[i] ? 0 : MAP_NOINIT) | MAP_DIRTY); fpr.MapRegV(tempregs[i], sregs[i] == dregs[i] ? MAP_DIRTY : MAP_NOINIT);
if (fpr.V(sregs[i]).IsSimpleReg()) { if (fpr.V(sregs[i]).IsSimpleReg()) {
CVTDQ2PS(fpr.VX(tempregs[i]), fpr.V(sregs[i])); CVTDQ2PS(fpr.VX(tempregs[i]), fpr.V(sregs[i]));
} else { } else {
@ -1834,7 +1834,7 @@ void Jit::Comp_Vsgn(MIPSOpcode op) {
} }
else else
{ {
fpr.MapRegV(dregs[i], (dregs[i] == sregs[i] ? 0 : MAP_NOINIT) | MAP_DIRTY); fpr.MapRegV(dregs[i], dregs[i] == sregs[i] ? MAP_DIRTY : MAP_NOINIT);
fpr.SpillLockV(dregs[i]); fpr.SpillLockV(dregs[i]);
tempxregs[i] = fpr.VX(dregs[i]); tempxregs[i] = fpr.VX(dregs[i]);
} }
@ -1892,7 +1892,7 @@ void Jit::Comp_Vocp(MIPSOpcode op) {
} }
else else
{ {
fpr.MapRegV(dregs[i], (dregs[i] == sregs[i] ? 0 : MAP_NOINIT) | MAP_DIRTY); fpr.MapRegV(dregs[i], dregs[i] == sregs[i] ? MAP_DIRTY : MAP_NOINIT);
fpr.SpillLockV(dregs[i]); fpr.SpillLockV(dregs[i]);
tempxregs[i] = fpr.VX(dregs[i]); tempxregs[i] = fpr.VX(dregs[i]);
} }
@ -2043,7 +2043,7 @@ void Jit::Comp_VV2Op(MIPSOpcode op) {
} }
else else
{ {
fpr.MapRegV(dregs[i], (dregs[i] == sregs[i] ? 0 : MAP_NOINIT) | MAP_DIRTY); fpr.MapRegV(dregs[i], dregs[i] == sregs[i] ? MAP_DIRTY : MAP_NOINIT);
fpr.SpillLockV(dregs[i]); fpr.SpillLockV(dregs[i]);
tempxregs[i] = fpr.VX(dregs[i]); tempxregs[i] = fpr.VX(dregs[i]);
} }
@ -2427,7 +2427,7 @@ void Jit::Comp_VScl(MIPSOpcode op) {
} }
else else
{ {
fpr.MapRegV(dregs[i], (dregs[i] == sregs[i] ? 0 : MAP_NOINIT) | MAP_DIRTY); fpr.MapRegV(dregs[i], dregs[i] == sregs[i] ? MAP_DIRTY : MAP_NOINIT);
fpr.SpillLockV(dregs[i]); fpr.SpillLockV(dregs[i]);
tempxregs[i] = fpr.VX(dregs[i]); tempxregs[i] = fpr.VX(dregs[i]);
} }
@ -2691,14 +2691,14 @@ void Jit::Comp_Vi2x(MIPSOpcode op) {
// Will be discarded on release. // Will be discarded on release.
vreg = fpr.GetTempV(); vreg = fpr.GetTempV();
} }
fpr.MapRegV(vreg, (vreg == sregs[0] ? 0 : MAP_NOINIT) | MAP_DIRTY); fpr.MapRegV(vreg, vreg == sregs[0] ? MAP_DIRTY : MAP_NOINIT);
fpr.SpillLockV(vreg); fpr.SpillLockV(vreg);
dst0 = fpr.VX(vreg); dst0 = fpr.VX(vreg);
} else { } else {
// Pair, let's check if we should use dregs[0] directly. No temp needed. // Pair, let's check if we should use dregs[0] directly. No temp needed.
int vreg = dregs[0]; int vreg = dregs[0];
if (IsOverlapSafeAllowS(dregs[0], 0, 2, sregs)) { if (IsOverlapSafeAllowS(dregs[0], 0, 2, sregs)) {
fpr.MapRegV(vreg, (vreg == sregs[0] ? 0 : MAP_NOINIT) | MAP_DIRTY); fpr.MapRegV(vreg, vreg == sregs[0] ? MAP_DIRTY : MAP_NOINIT);
fpr.SpillLockV(vreg); fpr.SpillLockV(vreg);
dst0 = fpr.VX(vreg); dst0 = fpr.VX(vreg);
} }
@ -2789,7 +2789,7 @@ void Jit::Comp_Vhoriz(MIPSOpcode op) {
X64Reg reg = XMM0; X64Reg reg = XMM0;
if (IsOverlapSafeAllowS(dregs[0], 0, n, sregs)) { if (IsOverlapSafeAllowS(dregs[0], 0, n, sregs)) {
fpr.MapRegV(dregs[0], (dregs[0] == sregs[0] ? 0 : MAP_NOINIT) | MAP_DIRTY); fpr.MapRegV(dregs[0], dregs[0] == sregs[0] ? MAP_DIRTY : MAP_NOINIT);
fpr.SpillLockV(dregs[0]); fpr.SpillLockV(dregs[0]);
reg = fpr.VX(dregs[0]); reg = fpr.VX(dregs[0]);
} }

14
Core/MIPS/x86/RegCacheFPU.cpp
View file

@ -93,7 +93,7 @@ void FPURegCache::ReleaseSpillLockV(const u8 *vec, VectorSize sz) {
} }
void FPURegCache::MapRegV(int vreg, int flags) { void FPURegCache::MapRegV(int vreg, int flags) {
MapReg(vreg + 32, (flags & MAP_NOINIT) == 0, (flags & MAP_DIRTY) != 0); MapReg(vreg + 32, (flags & MAP_NOINIT) != MAP_NOINIT, (flags & MAP_DIRTY) != 0);
} }
void FPURegCache::MapRegsV(int vec, VectorSize sz, int flags) { void FPURegCache::MapRegsV(int vec, VectorSize sz, int flags) {
@ -101,14 +101,14 @@ void FPURegCache::MapRegsV(int vec, VectorSize sz, int flags) {
GetVectorRegs(r, sz, vec); GetVectorRegs(r, sz, vec);
SpillLockV(r, sz); SpillLockV(r, sz);
for (int i = 0; i < GetNumVectorElements(sz); i++) { for (int i = 0; i < GetNumVectorElements(sz); i++) {
MapReg(r[i] + 32, (flags & MAP_NOINIT) == 0, (flags & MAP_DIRTY) != 0); MapReg(r[i] + 32, (flags & MAP_NOINIT) != MAP_NOINIT, (flags & MAP_DIRTY) != 0);
} }
} }
void FPURegCache::MapRegsV(const u8 *r, VectorSize sz, int flags) { void FPURegCache::MapRegsV(const u8 *r, VectorSize sz, int flags) {
SpillLockV(r, sz); SpillLockV(r, sz);
for (int i = 0; i < GetNumVectorElements(sz); i++) { for (int i = 0; i < GetNumVectorElements(sz); i++) {
MapReg(r[i] + 32, (flags & MAP_NOINIT) == 0, (flags & MAP_DIRTY) != 0); MapReg(r[i] + 32, (flags & MAP_NOINIT) != MAP_NOINIT, (flags & MAP_DIRTY) != 0);
} }
} }
@ -222,7 +222,7 @@ bool FPURegCache::TryMapRegsVS(const u8 *v, VectorSize vsz, int flags) {
} }
X64Reg xr; X64Reg xr;
if ((flags & MAP_NOINIT) == 0) { if ((flags & MAP_NOINIT) != MAP_NOINIT) {
xr = LoadRegsVS(v, n); xr = LoadRegsVS(v, n);
} else { } else {
xr = GetFreeXReg(); xr = GetFreeXReg();
@ -385,7 +385,7 @@ bool FPURegCache::TryMapDirtyInVS(const u8 *vd, VectorSize vdsz, const u8 *vs, V
bool success = TryMapRegsVS(vs, vssz, 0); bool success = TryMapRegsVS(vs, vssz, 0);
if (success) { if (success) {
SpillLockV(vs, vssz); SpillLockV(vs, vssz);
success = TryMapRegsVS(vd, vdsz, avoidLoad ? (MAP_NOINIT | MAP_DIRTY) : MAP_DIRTY); success = TryMapRegsVS(vd, vdsz, avoidLoad ? MAP_NOINIT : MAP_DIRTY);
} }
ReleaseSpillLockV(vs, vssz); ReleaseSpillLockV(vs, vssz);
@ -405,7 +405,7 @@ bool FPURegCache::TryMapDirtyInInVS(const u8 *vd, VectorSize vdsz, const u8 *vs,
} }
if (success) { if (success) {
SpillLockV(vt, vtsz); SpillLockV(vt, vtsz);
success = TryMapRegsVS(vd, vdsz, avoidLoad ? (MAP_NOINIT | MAP_DIRTY) : MAP_DIRTY); success = TryMapRegsVS(vd, vdsz, avoidLoad ? MAP_NOINIT : MAP_DIRTY);
} }
ReleaseSpillLockV(vs, vssz); ReleaseSpillLockV(vs, vssz);
ReleaseSpillLockV(vt, vtsz); ReleaseSpillLockV(vt, vtsz);
@ -442,7 +442,7 @@ void FPURegCache::SimpleRegV(const u8 v, int flags) {
vr.lane = 0; vr.lane = 0;
} else if (vr.lane != 0) { } else if (vr.lane != 0) {
// This will never end up in a register this way, so ignore dirty. // This will never end up in a register this way, so ignore dirty.
if ((flags & MAP_NOINIT)) { if ((flags & MAP_NOINIT) == MAP_NOINIT) {
// This will discard only this reg, and store the others. // This will discard only this reg, and store the others.
DiscardV(v); DiscardV(v);
} else { } else {

2
Core/MIPS/x86/RegCacheFPU.h
View file

@ -85,7 +85,7 @@ namespace MIPSComp {
enum { enum {
MAP_DIRTY = 1, MAP_DIRTY = 1,
MAP_NOINIT = 2, MAP_NOINIT = 2 | MAP_DIRTY,
}; };
// The PSP has 160 FP registers: 32 FPRs + 128 VFPU registers. // The PSP has 160 FP registers: 32 FPRs + 128 VFPU registers.