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Fix VMOV for Dregs and VSHL reg order.

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Unknown W. Brackets 2014-03-20 23:55:25 -07:00
parent 0da9c1851c
commit f3d38ee269
2 changed files with 4 additions and 3 deletions
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5
Common/ArmEmitter.cpp
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@ -1489,7 +1489,8 @@ void ARMXEmitter::VMSR(ARMReg Rt) {
void ARMXEmitter::VMOV(ARMReg Dest, Operand2 op2) void ARMXEmitter::VMOV(ARMReg Dest, Operand2 op2)
{ {
_assert_msg_(JIT, cpu_info.bVFPv3, "VMOV #imm requires VFPv3"); _assert_msg_(JIT, cpu_info.bVFPv3, "VMOV #imm requires VFPv3");
Write32(condition | (0xEB << 20) | EncodeVd(Dest) | (0xA << 8) | op2.Imm8VFP()); int sz = Dest >= D0 ? (1 << 8) : 0;
Write32(condition | (0xEB << 20) | EncodeVd(Dest) | (5 << 9) | sz | op2.Imm8VFP());
} }
void ARMXEmitter::VMOV(ARMReg Dest, ARMReg Src, bool high) void ARMXEmitter::VMOV(ARMReg Dest, ARMReg Src, bool high)
{ {
@ -2431,7 +2432,7 @@ void ARMXEmitter::VRSUBHN(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
Write32((0xF3 << 24) | (1 << 23) | ((encodedSize(Size) - 1) << 20) | EncodeVn(Vn) | EncodeVd(Vd) | \ Write32((0xF3 << 24) | (1 << 23) | ((encodedSize(Size) - 1) << 20) | EncodeVn(Vn) | EncodeVd(Vd) | \
(0x60 << 4) | EncodeVm(Vm)); (0x60 << 4) | EncodeVm(Vm));
} }
void ARMXEmitter::VSHL(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm) void ARMXEmitter::VSHL(u32 Size, ARMReg Vd, ARMReg Vm, ARMReg Vn)
{ {
_dbg_assert_msg_(JIT, Vd >= D0, "Pass invalid register to " __FUNCTION__); _dbg_assert_msg_(JIT, Vd >= D0, "Pass invalid register to " __FUNCTION__);
_dbg_assert_msg_(JIT, cpu_info.bNEON, "Can't use " __FUNCTION__ " when CPU doesn't support it"); _dbg_assert_msg_(JIT, cpu_info.bNEON, "Can't use " __FUNCTION__ " when CPU doesn't support it");

2
Common/ArmEmitter.h
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@ -722,7 +722,7 @@ public:
void VRSQRTE(u32 Size, ARMReg Vd, ARMReg Vm); void VRSQRTE(u32 Size, ARMReg Vd, ARMReg Vm);
void VRSQRTS(ARMReg Vd, ARMReg Vn, ARMReg Vm); void VRSQRTS(ARMReg Vd, ARMReg Vn, ARMReg Vm);
void VRSUBHN(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm); void VRSUBHN(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm);
void VSHL(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm); void VSHL(u32 Size, ARMReg Vd, ARMReg Vm, ARMReg Vn);
void VSUB(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm); void VSUB(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm);
void VSUBHN(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm); void VSUBHN(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm);
void VSUBL(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm); void VSUBL(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm);