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arm64jit: Use TBZ/TBNZ for vfpu branch as well.

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Unknown W. Brackets 2017-12-29 14:43:53 -08:00
parent 3b4917a308
commit ee236743f0
1 changed files with 15 additions and 17 deletions
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28
Core/MIPS/ARM64/Arm64CompBranch.cpp
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@ -419,28 +419,26 @@ void Arm64Jit::BranchVFPUFlag(MIPSOpcode op, CCFlags cc, bool likely) {
int imm3 = (op >> 18) & 7; int imm3 = (op >> 18) & 7;
// TODO: Maybe could use TBZ?
gpr.MapReg(MIPS_REG_VFPUCC); gpr.MapReg(MIPS_REG_VFPUCC);
TSTI2R(gpr.R(MIPS_REG_VFPUCC), 1 << imm3, SCRATCH1);
Arm64Gen::FixupBranch ptr; Arm64Gen::FixupBranch ptr;
js.inDelaySlot = true; if (likely || delaySlotIsNice || delaySlotIsBranch) {
if (!likely) // FlushAll() won't actually change the reg.
{ ARM64Reg ar = gpr.R(MIPS_REG_VFPUCC);
if (!delaySlotIsNice && !delaySlotIsBranch)
CompileDelaySlot(DELAYSLOT_SAFE_FLUSH);
else
FlushAll(); FlushAll();
if (cc == CC_EQ) {
ptr = TBZ(ar, imm3);
} else {
ptr = TBNZ(ar, imm3);
}
} else {
TSTI2R(gpr.R(MIPS_REG_VFPUCC), 1 << imm3, SCRATCH1);
CompileDelaySlot(DELAYSLOT_SAFE_FLUSH);
ptr = B(cc); ptr = B(cc);
} }
else
{ if (likely && !delaySlotIsBranch) {
FlushAll();
ptr = B(cc);
if (!delaySlotIsBranch)
CompileDelaySlot(DELAYSLOT_FLUSH); CompileDelaySlot(DELAYSLOT_FLUSH);
} }
js.inDelaySlot = false;
// Take the branch // Take the branch
WriteExit(targetAddr, js.nextExit++); WriteExit(targetAddr, js.nextExit++);