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JIT: Ignore branches in delay slots. Not sure if this is 100% correct.

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This commit is contained in:
Henrik Rydgård 2012-12-26 08:37:53 +01:00
parent 1328413dfc
commit ed68dea0d5
2 changed files with 26 additions and 1 deletions
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26
Core/MIPS/x86/CompBranch.cpp
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@ -61,6 +61,10 @@ static u64 saved_flags;
void Jit::BranchRSRTComp(u32 op, Gen::CCFlags cc, bool likely)
{
if (js.inDelaySlot) {
ERROR_LOG(JIT, "Branch in delay slot at %08x", js.compilerPC);
return;
}
int offset = (signed short)(op&0xFFFF)<<2;
int rt = _RT;
int rs = _RS;
@ -119,6 +123,10 @@ void Jit::BranchRSRTComp(u32 op, Gen::CCFlags cc, bool likely)
void Jit::BranchRSZeroComp(u32 op, Gen::CCFlags cc, bool likely)
{
if (js.inDelaySlot) {
ERROR_LOG(JIT, "Branch in delay slot at %08x", js.compilerPC);
return;
}
int offset = (signed short)(op&0xFFFF)<<2;
int rs = _RS;
u32 targetAddr = js.compilerPC + offset + 4;
@ -208,6 +216,10 @@ void Jit::Comp_RelBranchRI(u32 op)
// If likely is set, discard the branch slot if NOT taken.
void Jit::BranchFPFlag(u32 op, Gen::CCFlags cc, bool likely)
{
if (js.inDelaySlot) {
ERROR_LOG(JIT, "Branch in delay slot at %08x", js.compilerPC);
return;
}
int offset = (signed short)(op & 0xFFFF) << 2;
u32 targetAddr = js.compilerPC + offset + 4;
@ -273,6 +285,10 @@ void Jit::Comp_FPUBranch(u32 op)
// If likely is set, discard the branch slot if NOT taken.
void Jit::BranchVFPUFlag(u32 op, Gen::CCFlags cc, bool likely)
{
if (js.inDelaySlot) {
ERROR_LOG(JIT, "Branch in delay slot at %08x", js.compilerPC);
return;
}
int offset = (signed short)(op & 0xFFFF) << 2;
u32 targetAddr = js.compilerPC + offset + 4;
@ -346,10 +362,14 @@ void Jit::Comp_VBranch(u32 op)
void Jit::Comp_Jump(u32 op)
{
if (js.inDelaySlot) {
ERROR_LOG(JIT, "Branch in delay slot at %08x", js.compilerPC);
return;
}
u32 off = ((op & 0x3FFFFFF) << 2);
u32 targetAddr = (js.compilerPC & 0xF0000000) | off;
//Delay slot
CompileAt(js.compilerPC + 4);
CompileAt(js.compilerPC + 4);
FlushAll();
switch (op >> 26)
@ -374,6 +394,10 @@ static u32 savedPC;
void Jit::Comp_JumpReg(u32 op)
{
if (js.inDelaySlot) {
ERROR_LOG(JIT, "Branch in delay slot at %08x", js.compilerPC);
return;
}
int rs = _RS;
u32 delaySlotOp = Memory::ReadUnchecked_U32(js.compilerPC + 4);

1
Core/MIPS/x86/RegCache.cpp
View file

@ -287,6 +287,7 @@ void GPRRegCache::BindToRegister(int i, bool doLoad, bool makeDirty)
{
if (i != j && regs[j].location.IsSimpleReg() && regs[j].location.GetSimpleReg() == xr)
{
ERROR_LOG(JIT, "BindToRegister: Strange condition");
Crash();
}
}