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arm64jit: Cleanup method names, temp discard.
This way MapDirtyIn won't accidentally discard temps.
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parent
eb35e88288
commit
e7ac672522
3 changed files with 25 additions and 18 deletions
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@ -250,7 +250,7 @@ namespace MIPSComp {
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SetJumpTarget(skip);
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}
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gpr.ReleaseSpillLocks();
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gpr.ReleaseSpillLocksAndDiscardTemps();
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}
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void Arm64Jit::Comp_ITypeMem(MIPSOpcode op) {
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@ -311,7 +311,7 @@ namespace MIPSComp {
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gpr.MapRegAsPointer(rs);
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// For a store, try to avoid mapping a reg if not needed.
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targetReg = load ? INVALID_REG : gpr.MapTempImm(rt);
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targetReg = load ? INVALID_REG : gpr.TryMapTempImm(rt);
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if (targetReg == INVALID_REG) {
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gpr.MapReg(rt, load ? MAP_NOINIT : 0);
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targetReg = gpr.R(rt);
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@ -327,12 +327,12 @@ namespace MIPSComp {
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case 41: STRH(INDEX_UNSIGNED, targetReg, gpr.RPtr(rs), offset); break;
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case 40: STRB(INDEX_UNSIGNED, targetReg, gpr.RPtr(rs), offset); break;
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}
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gpr.ReleaseSpillLocks();
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gpr.ReleaseSpillLocksAndDiscardTemps();
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break;
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}
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}
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if (!load && gpr.IsImm(rt) && gpr.MapTempImm(rt) != INVALID_REG) {
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if (!load && gpr.IsImm(rt) && gpr.TryMapTempImm(rt) != INVALID_REG) {
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// We're storing an immediate value, let's see if we can optimize rt.
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if (!gpr.IsImm(rs) || offset == 0) {
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// In this case, we're always going to need rs mapped, which may flush the temp imm.
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@ -340,7 +340,7 @@ namespace MIPSComp {
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gpr.MapIn(rs);
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}
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targetReg = gpr.MapTempImm(rt);
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targetReg = gpr.TryMapTempImm(rt);
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}
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if (gpr.IsImm(rs) && Memory::IsValidAddress(iaddr)) {
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@ -304,7 +304,7 @@ ARM64Reg Arm64RegCache::FindBestToSpill(bool unusedOnly, bool *clobbered) {
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return INVALID_REG;
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}
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ARM64Reg Arm64RegCache::MapTempImm(MIPSGPReg r) {
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ARM64Reg Arm64RegCache::TryMapTempImm(MIPSGPReg r) {
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// If already mapped, no need for a temporary.
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if (IsMapped(r)) {
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return R(r);
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@ -459,7 +459,7 @@ void Arm64RegCache::MapInIn(MIPSGPReg rd, MIPSGPReg rs) {
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SpillLock(rd, rs);
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MapReg(rd);
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MapReg(rs);
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ReleaseSpillLocks();
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ReleaseSpillLock(rd, rs);
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}
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void Arm64RegCache::MapDirtyIn(MIPSGPReg rd, MIPSGPReg rs, bool avoidLoad) {
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@ -467,7 +467,7 @@ void Arm64RegCache::MapDirtyIn(MIPSGPReg rd, MIPSGPReg rs, bool avoidLoad) {
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bool load = !avoidLoad || rd == rs;
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MapReg(rd, load ? MAP_DIRTY : MAP_NOINIT);
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MapReg(rs);
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ReleaseSpillLocks();
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ReleaseSpillLock(rd, rs);
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}
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void Arm64RegCache::MapDirtyInIn(MIPSGPReg rd, MIPSGPReg rs, MIPSGPReg rt, bool avoidLoad) {
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@ -476,7 +476,7 @@ void Arm64RegCache::MapDirtyInIn(MIPSGPReg rd, MIPSGPReg rs, MIPSGPReg rt, bool
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MapReg(rd, load ? MAP_DIRTY : MAP_NOINIT);
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MapReg(rt);
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MapReg(rs);
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ReleaseSpillLocks();
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ReleaseSpillLock(rd, rs, rt);
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}
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void Arm64RegCache::MapDirtyDirtyIn(MIPSGPReg rd1, MIPSGPReg rd2, MIPSGPReg rs, bool avoidLoad) {
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@ -486,7 +486,7 @@ void Arm64RegCache::MapDirtyDirtyIn(MIPSGPReg rd1, MIPSGPReg rd2, MIPSGPReg rs,
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MapReg(rd1, load1 ? MAP_DIRTY : MAP_NOINIT);
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MapReg(rd2, load2 ? MAP_DIRTY : MAP_NOINIT);
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MapReg(rs);
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ReleaseSpillLocks();
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ReleaseSpillLock(rd1, rd2, rs);
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}
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void Arm64RegCache::MapDirtyDirtyInIn(MIPSGPReg rd1, MIPSGPReg rd2, MIPSGPReg rs, MIPSGPReg rt, bool avoidLoad) {
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@ -497,7 +497,7 @@ void Arm64RegCache::MapDirtyDirtyInIn(MIPSGPReg rd1, MIPSGPReg rd2, MIPSGPReg rs
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MapReg(rd2, load2 ? MAP_DIRTY : MAP_NOINIT);
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MapReg(rt);
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MapReg(rs);
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ReleaseSpillLocks();
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ReleaseSpillLock(rd1, rd2, rs, rt);
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}
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void Arm64RegCache::FlushArmReg(ARM64Reg r) {
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@ -872,7 +872,7 @@ void Arm64RegCache::SpillLock(MIPSGPReg r1, MIPSGPReg r2, MIPSGPReg r3, MIPSGPRe
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if (r4 != MIPS_REG_INVALID) mr[r4].spillLock = true;
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}
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void Arm64RegCache::ReleaseSpillLocks() {
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void Arm64RegCache::ReleaseSpillLocksAndDiscardTemps() {
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for (int i = 0; i < NUM_MIPSREG; i++) {
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if (!mr[i].isStatic)
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mr[i].spillLock = false;
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@ -882,9 +882,15 @@ void Arm64RegCache::ReleaseSpillLocks() {
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}
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}
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void Arm64RegCache::ReleaseSpillLock(MIPSGPReg reg) {
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if (!mr[reg].isStatic)
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mr[reg].spillLock = false;
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void Arm64RegCache::ReleaseSpillLock(MIPSGPReg r1, MIPSGPReg r2, MIPSGPReg r3, MIPSGPReg r4) {
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if (!mr[r1].isStatic)
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mr[r1].spillLock = false;
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if (r2 != MIPS_REG_INVALID && !mr[r2].isStatic)
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mr[r2].spillLock = false;
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if (r3 != MIPS_REG_INVALID && !mr[r3].isStatic)
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mr[r3].spillLock = false;
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if (r4 != MIPS_REG_INVALID && !mr[r4].isStatic)
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mr[r4].spillLock = false;
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}
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ARM64Reg Arm64RegCache::R(MIPSGPReg mipsReg) {
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@ -92,8 +92,8 @@ public:
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// Protect the arm register containing a MIPS register from spilling, to ensure that
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// it's being kept allocated.
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void SpillLock(MIPSGPReg reg, MIPSGPReg reg2 = MIPS_REG_INVALID, MIPSGPReg reg3 = MIPS_REG_INVALID, MIPSGPReg reg4 = MIPS_REG_INVALID);
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void ReleaseSpillLock(MIPSGPReg reg);
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void ReleaseSpillLocks();
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void ReleaseSpillLock(MIPSGPReg reg, MIPSGPReg reg2 = MIPS_REG_INVALID, MIPSGPReg reg3 = MIPS_REG_INVALID, MIPSGPReg reg4 = MIPS_REG_INVALID);
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void ReleaseSpillLocksAndDiscardTemps();
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void SetImm(MIPSGPReg reg, u64 immVal);
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bool IsImm(MIPSGPReg reg) const;
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@ -102,7 +102,8 @@ public:
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// Optimally set a register to an imm value (possibly using another register.)
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void SetRegImm(Arm64Gen::ARM64Reg reg, u64 imm);
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Arm64Gen::ARM64Reg MapTempImm(MIPSGPReg);
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// May fail and return INVALID_REG if it needs flushing.
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Arm64Gen::ARM64Reg TryMapTempImm(MIPSGPReg);
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// Returns an ARM register containing the requested MIPS register.
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Arm64Gen::ARM64Reg MapReg(MIPSGPReg reg, int mapFlags = 0);
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