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Add swl/swr to the x86 jit.

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This commit is contained in:
Unknown W. Brackets 2013-07-04 17:34:56 -07:00
parent 203daf955b
commit e27ab6fa11
2 changed files with 65 additions and 18 deletions
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81
Core/MIPS/x86/CompLoadStore.cpp
View file

@ -102,7 +102,7 @@ namespace MIPSComp
gpr.UnlockAll();
}
void Jit::CompITypeMemUnpairedLR(u32 op)
void Jit::CompITypeMemUnpairedLR(u32 op, bool isStore)
{
CONDITIONAL_DISABLE;
int o = op>>26;
@ -113,7 +113,7 @@ namespace MIPSComp
gpr.FlushLockX(ECX, EDX);
gpr.Lock(rt);
gpr.BindToRegister(rt, true, true);
gpr.BindToRegister(rt, true, !isStore);
// Grab the offset from alignment for shifting (<< 3 for bytes -> bits.)
MOV(32, R(ECX), gpr.R(rs));
@ -121,20 +121,33 @@ namespace MIPSComp
AND(32, R(ECX), Imm32(3));
SHL(32, R(ECX), Imm8(3));
JitSafeMem safe(this, rs, offset, ~3);
safe.SetFar();
OpArg src;
bool ready = false;
if (safe.PrepareRead(src, 4))
{
if (!src.IsSimpleReg(EAX))
MOV(32, R(EAX), src);
JitSafeMem safe(this, rs, offset, ~3);
safe.SetFar();
OpArg src;
if (safe.PrepareRead(src, 4))
{
if (!src.IsSimpleReg(EAX))
MOV(32, R(EAX), src);
CompITypeMemUnpairedLRInner(op);
CompITypeMemUnpairedLRInner(op);
}
if (safe.PrepareSlowRead((void *) &Memory::Read_U32))
CompITypeMemUnpairedLRInner(op);
safe.Finish();
}
// For store ops, write EDX back to memory.
if (isStore)
{
JitSafeMem safe(this, rs, offset, ~3);
OpArg dest;
if (safe.PrepareWrite(dest, 4))
MOV(32, dest, R(EDX));
if (safe.PrepareSlowWrite())
safe.DoSlowWrite((void *) &Memory::Write_U32, R(EDX));
safe.Finish();
}
if (safe.PrepareSlowRead((void *) &Memory::Read_U32))
CompITypeMemUnpairedLRInner(op);
safe.Finish();
gpr.UnlockAll();
gpr.UnlockAllX();
@ -178,6 +191,40 @@ namespace MIPSComp
OR(32, gpr.R(rt), R(EAX));
break;
case 42: //swl
// First clear the target memory bits.
MOV(32, R(EDX), Imm32(0xffffff00));
SHL(32, R(EDX), R(CL));
AND(32, R(EAX), R(EDX));
// Flip the shift, and adjust the shift in a temporary.
MOV(32, R(EDX), Imm32(24));
SUB(32, R(EDX), R(ECX));
MOV(32, R(ECX), R(EDX));
MOV(32, R(EDX), gpr.R(rt));
SHR(32, R(EDX), R(CL));
OR(32, R(EDX), R(EAX));
break;
case 46: //swr
// Adjust the shift to the bits we want.
MOV(32, R(EDX), gpr.R(rt));
SHL(32, R(EDX), R(CL));
PUSH(EDX);
// Clear the target bits we're replacing.
MOV(32, R(EDX), Imm32(24));
SUB(32, R(EDX), R(ECX));
MOV(32, R(ECX), R(EDX));
MOV(32, R(EDX), Imm32(0x00ffffff));
SHR(32, R(EDX), R(CL));
AND(32, R(EAX), R(EDX));
POP(EDX);
OR(32, R(EDX), R(EAX));
break;
default:
_dbg_assert_msg_(JIT, 0, "Unsupported left/right load/store instruction.");
}
@ -241,7 +288,7 @@ namespace MIPSComp
CompITypeMemRead(nextOp, 32, &XEmitter::MOVZX, (void *) &Memory::Read_U32);
}
else
CompITypeMemUnpairedLR(op);
CompITypeMemUnpairedLR(op, false);
}
break;
@ -257,7 +304,7 @@ namespace MIPSComp
CompITypeMemRead(op, 32, &XEmitter::MOVZX, (void *) &Memory::Read_U32);
}
else
CompITypeMemUnpairedLR(op);
CompITypeMemUnpairedLR(op, false);
}
break;
@ -273,7 +320,7 @@ namespace MIPSComp
CompITypeMemWrite(nextOp, 32, (void *) &Memory::Write_U32);
}
else
Comp_Generic(op);
CompITypeMemUnpairedLR(op, true);
}
break;
@ -289,7 +336,7 @@ namespace MIPSComp
CompITypeMemWrite(op, 32, (void *) &Memory::Write_U32);
}
else
Comp_Generic(op);
CompITypeMemUnpairedLR(op, true);
}
break;

2
Core/MIPS/x86/Jit.h
View file

@ -273,7 +273,7 @@ private:
void CompShiftVar(u32 op, void (XEmitter::*shift)(int, OpArg, OpArg), u32 (*doImm)(const u32, const u32));
void CompITypeMemRead(u32 op, u32 bits, void (XEmitter::*mov)(int, int, X64Reg, OpArg), void *safeFunc);
void CompITypeMemWrite(u32 op, u32 bits, void *safeFunc);
void CompITypeMemUnpairedLR(u32 op);
void CompITypeMemUnpairedLR(u32 op, bool isStore);
void CompITypeMemUnpairedLRInner(u32 op);
void CompFPTriArith(u32 op, void (XEmitter::*arith)(X64Reg reg, OpArg), bool orderMatters);