From dae9df38295f6034b416a0b62d74c6c414e67b15 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Henrik=20Rydg=C3=A5rd?= <hrydgard@gmail.com>
Date: Sun, 19 Jul 2020 17:22:33 +0200
Subject: [PATCH] Fix a bug in crashhandler where we could end up disassembling
 far too much.

---
 Common/x64Analyzer.cpp            | 8 ++++++--
 Common/x64Analyzer.h              | 1 +
 Core/MIPS/JitCommon/JitCommon.cpp | 7 ++++++-
 Core/MemFault.cpp                 | 8 ++++----
 4 files changed, 17 insertions(+), 7 deletions(-)

diff --git a/Common/x64Analyzer.cpp b/Common/x64Analyzer.cpp
index 0d04346c04..1a9d236db6 100644
--- a/Common/x64Analyzer.cpp
+++ b/Common/x64Analyzer.cpp
@@ -15,7 +15,8 @@
 // Official SVN repository and contact information can be found at
 // http://code.google.com/p/dolphin-emu/
 
-#include "x64Analyzer.h"
+#include "Common/Log.h"
+#include "Common/x64Analyzer.h"
 
 bool X86AnalyzeMOV(const unsigned char *codePtr, LSInstructionInfo &info)
 {
@@ -183,8 +184,11 @@ bool X86AnalyzeMOV(const unsigned char *codePtr, LSInstructionInfo &info)
 		case MOVE_REG_TO_MEM: //move reg to memory
 			break;
 
+		case MOVE_MEM_TO_REG:
+			break;
+
 		default:
-			PanicAlert("Unhandled disasm case in write handler!\n\nPlease implement or avoid.");
+			ERROR_LOG(CPU, "Unhandled disasm case in write handler!\n\nPlease implement or avoid.");
 			return false;
 		}
 	}
diff --git a/Common/x64Analyzer.h b/Common/x64Analyzer.h
index 8ba78005e5..f9a35e785c 100644
--- a/Common/x64Analyzer.h
+++ b/Common/x64Analyzer.h
@@ -53,6 +53,7 @@ enum {
 	MOVE_8BIT	    = 0xC6, //move 8-bit immediate
 	MOVE_16_32BIT   = 0xC7, //move 16 or 32-bit immediate
 	MOVE_REG_TO_MEM = 0x89, //move reg to memory
+	MOVE_MEM_TO_REG = 0x8B, //move memory to reg
 };
 
 enum AccessType {
diff --git a/Core/MIPS/JitCommon/JitCommon.cpp b/Core/MIPS/JitCommon/JitCommon.cpp
index baf26f6bcc..697733ec1d 100644
--- a/Core/MIPS/JitCommon/JitCommon.cpp
+++ b/Core/MIPS/JitCommon/JitCommon.cpp
@@ -246,7 +246,12 @@ std::vector<std::string> DisassembleX86(const u8 *data, int size) {
 
 	int int3_count = 0;
 	while (ud_disassemble(&ud_obj) != 0) {
-		std::string str = ud_insn_asm(&ud_obj);
+		const char *buf = ud_insn_asm(&ud_obj);
+		if (!buf) {
+			lines.push_back("[bad]");
+			continue;
+		}
+		std::string str = buf;
 		if (str == "int3") {
 			int3_count++;
 		} else {
diff --git a/Core/MemFault.cpp b/Core/MemFault.cpp
index 104be4af59..5e8748a333 100644
--- a/Core/MemFault.cpp
+++ b/Core/MemFault.cpp
@@ -114,25 +114,25 @@ bool HandleFault(uintptr_t hostAddress, void *ctx) {
 	// X86, X86-64. Variable instruction size so need to analyze the mov instruction in detail.
 
 	// To ignore the access, we need to disassemble the instruction and modify context->CTX_PC
-	LSInstructionInfo info;
+	LSInstructionInfo info{};
 	success = X86AnalyzeMOV(codePtr, info);
 	instructionSize = info.instructionSize;
 #elif PPSSPP_ARCH(ARM64)
 	uint32_t word;
 	memcpy(&word, codePtr, 4);
 	// To ignore the access, we need to disassemble the instruction and modify context->CTX_PC
-	Arm64LSInstructionInfo info;
+	Arm64LSInstructionInfo info{};
 	success = Arm64AnalyzeLoadStore((uint64_t)codePtr, word, &info);
 #elif PPSSPP_ARCH(ARM)
 	uint32_t word;
 	memcpy(&word, codePtr, 4);
 	// To ignore the access, we need to disassemble the instruction and modify context->CTX_PC
-	ArmLSInstructionInfo info;
+	ArmLSInstructionInfo info{};
 	success = ArmAnalyzeLoadStore((uint32_t)codePtr, word, &info);
 #endif
 
 	std::string disassembly;
-	if (DisassembleNativeAt(codePtr, instructionSize, &disassembly)) {
+	if (success && DisassembleNativeAt(codePtr, instructionSize, &disassembly)) {
 		infoString += disassembly + "\n";
 	}