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ARM: Fix divide by 0 in software divide used on CPUs without HW divide.

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This commit is contained in:
Henrik Rydgard 2013-11-15 20:24:01 +01:00
parent 6be534ca18
commit d17a5fefea
1 changed files with 5 additions and 9 deletions
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14
Core/MIPS/ARM/ArmCompALU.cpp
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@ -772,19 +772,15 @@ namespace MIPSComp
MUL(R0, gpr.R(rt), gpr.R(MIPS_REG_LO));
SUB(gpr.R(MIPS_REG_HI), gpr.R(rs), Operand2(R0));
} else {
DISABLE;
// If rt is 0, we either caught it above, or it's not an imm.
bool skipZero = gpr.IsImm(rt);
gpr.MapDirtyDirtyInIn(MIPS_REG_LO, MIPS_REG_HI, rs, rt);
MOV(R0, gpr.R(rt));
FixupBranch skipper;
if (!skipZero) {
CMP(gpr.R(rt), 0);
SetCC(CC_EQ);
// Just set to a really high number, can't divide by zero.
MVN(R0, 0);
SetCC(CC_AL);
skipper = B_CC(CC_EQ);
}
// Double R0 until it would be (but isn't) bigger than the numerator.
@ -811,15 +807,15 @@ namespace MIPSComp
CMP(R0, gpr.R(rt));
B_CC(CC_HS, subLoop);
FixupBranch zeroSkip = B();
// We didn't change rt. If it was 0, then clear HI and LO.
if (!skipZero) {
CMP(gpr.R(rt), 0);
SetCC(CC_EQ);
SetJumpTarget(skipper);
// TODO: Is this correct?
MOV(gpr.R(MIPS_REG_LO), 0);
MOV(gpr.R(MIPS_REG_HI), 0);
SetCC(CC_AL);
}
SetJumpTarget(zeroSkip);
}
break;