diff --git a/CMakeLists.txt b/CMakeLists.txt
index aedacf9563..b018c10f2a 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -1342,6 +1342,8 @@ add_library(${CoreLibName} ${CoreLinkType}
Core/MIPS/JitCommon/NativeJit.h
Core/MIPS/JitCommon/JitBlockCache.cpp
Core/MIPS/JitCommon/JitBlockCache.h
+ Core/MIPS/JitCommon/JitState.cpp
+ Core/MIPS/JitCommon/JitState.h
Core/MIPS/MIPS.cpp
Core/MIPS/MIPS.h
Core/MIPS/MIPSAnalyst.cpp
diff --git a/Core/Core.vcxproj b/Core/Core.vcxproj
index bc90969b8b..754779a961 100644
--- a/Core/Core.vcxproj
+++ b/Core/Core.vcxproj
@@ -415,6 +415,7 @@
+
@@ -718,4 +719,4 @@
-
+
\ No newline at end of file
diff --git a/Core/Core.vcxproj.filters b/Core/Core.vcxproj.filters
index 214cc00400..9a3310850b 100644
--- a/Core/Core.vcxproj.filters
+++ b/Core/Core.vcxproj.filters
@@ -593,6 +593,9 @@
Util
+
+ MIPS\JitCommon
+
@@ -1122,4 +1125,4 @@
-
+
\ No newline at end of file
diff --git a/Core/MIPS/ARM/ArmJit.h b/Core/MIPS/ARM/ArmJit.h
index 1712ee025f..cc37f27eaa 100644
--- a/Core/MIPS/ARM/ArmJit.h
+++ b/Core/MIPS/ARM/ArmJit.h
@@ -34,36 +34,6 @@
namespace MIPSComp
{
-struct ArmJitOptions
-{
- ArmJitOptions() {
- enableBlocklink = true;
- downcountInRegister = true;
- useBackJump = false;
- useForwardJump = false;
- cachePointers = true;
- immBranches = false;
- continueBranches = false;
- continueJumps = false;
- continueMaxInstructions = 300;
-
- useNEONVFPU = false; // true
- if (!cpu_info.bNEON)
- useNEONVFPU = false;
- }
-
- bool useNEONVFPU;
- bool enableBlocklink;
- bool downcountInRegister;
- bool useBackJump;
- bool useForwardJump;
- bool cachePointers;
- bool immBranches;
- bool continueBranches;
- bool continueJumps;
- int continueMaxInstructions;
-};
-
class ArmJit : public ArmGen::ARMXCodeBlock
{
public:
@@ -305,7 +275,7 @@ private:
void Comp_ITypeMemLR(MIPSOpcode op, bool load);
JitBlockCache blocks;
- ArmJitOptions jo;
+ JitOptions jo;
JitState js;
ArmRegCache gpr;
diff --git a/Core/MIPS/ARM/ArmRegCache.cpp b/Core/MIPS/ARM/ArmRegCache.cpp
index 9e36c7f64c..2ab327834f 100644
--- a/Core/MIPS/ARM/ArmRegCache.cpp
+++ b/Core/MIPS/ARM/ArmRegCache.cpp
@@ -29,7 +29,7 @@
using namespace ArmGen;
using namespace ArmJitConstants;
-ArmRegCache::ArmRegCache(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::ArmJitOptions *jo) : mips_(mips), js_(js), jo_(jo) {
+ArmRegCache::ArmRegCache(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::JitOptions *jo) : mips_(mips), js_(js), jo_(jo) {
}
void ArmRegCache::Init(ARMXEmitter *emitter) {
diff --git a/Core/MIPS/ARM/ArmRegCache.h b/Core/MIPS/ARM/ArmRegCache.h
index d2f6ba393e..00dbd709dc 100644
--- a/Core/MIPS/ARM/ArmRegCache.h
+++ b/Core/MIPS/ARM/ArmRegCache.h
@@ -82,13 +82,13 @@ struct RegMIPS {
};
namespace MIPSComp {
- struct ArmJitOptions;
+ struct JitOptions;
struct JitState;
}
class ArmRegCache {
public:
- ArmRegCache(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::ArmJitOptions *jo);
+ ArmRegCache(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::JitOptions *jo);
~ArmRegCache() {}
void Init(ArmGen::ARMXEmitter *emitter);
@@ -143,7 +143,7 @@ private:
MIPSState *mips_;
ArmGen::ARMXEmitter *emit_;
MIPSComp::JitState *js_;
- MIPSComp::ArmJitOptions *jo_;
+ MIPSComp::JitOptions *jo_;
u32 compilerPC_;
enum {
diff --git a/Core/MIPS/ARM/ArmRegCacheFPU.cpp b/Core/MIPS/ARM/ArmRegCacheFPU.cpp
index 6c03a19b67..cde3cb11e6 100644
--- a/Core/MIPS/ARM/ArmRegCacheFPU.cpp
+++ b/Core/MIPS/ARM/ArmRegCacheFPU.cpp
@@ -27,7 +27,7 @@
using namespace ArmGen;
using namespace ArmJitConstants;
-ArmRegCacheFPU::ArmRegCacheFPU(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::ArmJitOptions *jo) : mips_(mips), vr(mr + 32), js_(js), jo_(jo), initialReady(false) {
+ArmRegCacheFPU::ArmRegCacheFPU(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::JitOptions *jo) : mips_(mips), vr(mr + 32), js_(js), jo_(jo), initialReady(false) {
if (cpu_info.bNEON) {
numARMFpuReg_ = 32;
} else {
diff --git a/Core/MIPS/ARM/ArmRegCacheFPU.h b/Core/MIPS/ARM/ArmRegCacheFPU.h
index 03efc32157..59bbd71de7 100644
--- a/Core/MIPS/ARM/ArmRegCacheFPU.h
+++ b/Core/MIPS/ARM/ArmRegCacheFPU.h
@@ -77,13 +77,13 @@ struct FPURegMIPS {
};
namespace MIPSComp {
- struct ArmJitOptions;
+ struct JitOptions;
struct JitState;
}
class ArmRegCacheFPU {
public:
- ArmRegCacheFPU(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::ArmJitOptions *jo);
+ ArmRegCacheFPU(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::JitOptions *jo);
~ArmRegCacheFPU() {}
void Init(ArmGen::ARMXEmitter *emitter);
@@ -191,7 +191,7 @@ private:
MIPSState *mips_;
ArmGen::ARMXEmitter *emit_;
MIPSComp::JitState *js_;
- MIPSComp::ArmJitOptions *jo_;
+ MIPSComp::JitOptions *jo_;
int numARMFpuReg_;
int qTime_;
diff --git a/Core/MIPS/ARM64/Arm64Jit.h b/Core/MIPS/ARM64/Arm64Jit.h
index a9e9d16e84..7966e53662 100644
--- a/Core/MIPS/ARM64/Arm64Jit.h
+++ b/Core/MIPS/ARM64/Arm64Jit.h
@@ -34,32 +34,6 @@
namespace MIPSComp
{
-struct Arm64JitOptions
-{
- Arm64JitOptions() {
- enableBlocklink = true;
- useBackJump = false;
- useForwardJump = false;
- cachePointers = true;
- immBranches = false;
- continueBranches = false;
- continueJumps = false;
- continueMaxInstructions = 300;
-
- useASIMDVFPU = false; // true
- }
-
- bool useASIMDVFPU;
- bool enableBlocklink;
- bool useBackJump;
- bool useForwardJump;
- bool cachePointers;
- bool immBranches;
- bool continueBranches;
- bool continueJumps;
- int continueMaxInstructions;
-};
-
class Arm64Jit : public Arm64Gen::ARM64CodeBlock
{
public:
@@ -263,7 +237,7 @@ private:
void Comp_ITypeMemLR(MIPSOpcode op, bool load);
JitBlockCache blocks;
- Arm64JitOptions jo;
+ JitOptions jo;
JitState js;
Arm64RegCache gpr;
diff --git a/Core/MIPS/ARM64/Arm64RegCache.cpp b/Core/MIPS/ARM64/Arm64RegCache.cpp
index cf75984c89..8337372185 100644
--- a/Core/MIPS/ARM64/Arm64RegCache.cpp
+++ b/Core/MIPS/ARM64/Arm64RegCache.cpp
@@ -29,7 +29,7 @@
using namespace Arm64Gen;
using namespace Arm64JitConstants;
-Arm64RegCache::Arm64RegCache(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::Arm64JitOptions *jo) : mips_(mips), js_(js), jo_(jo) {
+Arm64RegCache::Arm64RegCache(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::JitOptions *jo) : mips_(mips), js_(js), jo_(jo) {
}
void Arm64RegCache::Init(ARM64XEmitter *emitter) {
diff --git a/Core/MIPS/ARM64/Arm64RegCache.h b/Core/MIPS/ARM64/Arm64RegCache.h
index 0b4edf232a..b0572373c0 100644
--- a/Core/MIPS/ARM64/Arm64RegCache.h
+++ b/Core/MIPS/ARM64/Arm64RegCache.h
@@ -85,13 +85,13 @@ struct RegMIPS {
};
namespace MIPSComp {
- struct Arm64JitOptions;
+ struct JitOptions;
struct JitState;
}
class Arm64RegCache {
public:
- Arm64RegCache(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::Arm64JitOptions *jo);
+ Arm64RegCache(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::JitOptions *jo);
~Arm64RegCache() {}
void Init(Arm64Gen::ARM64XEmitter *emitter);
@@ -146,7 +146,7 @@ private:
MIPSState *mips_;
Arm64Gen::ARM64XEmitter *emit_;
MIPSComp::JitState *js_;
- MIPSComp::Arm64JitOptions *jo_;
+ MIPSComp::JitOptions *jo_;
u32 compilerPC_;
enum {
diff --git a/Core/MIPS/ARM64/Arm64RegCacheFPU.cpp b/Core/MIPS/ARM64/Arm64RegCacheFPU.cpp
index efa7942dc6..6754885f05 100644
--- a/Core/MIPS/ARM64/Arm64RegCacheFPU.cpp
+++ b/Core/MIPS/ARM64/Arm64RegCacheFPU.cpp
@@ -27,7 +27,7 @@
using namespace Arm64Gen;
using namespace Arm64JitConstants;
-Arm64RegCacheFPU::Arm64RegCacheFPU(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::Arm64JitOptions *jo) : mips_(mips), vr(mr + 32), js_(js), jo_(jo), initialReady(false) {
+Arm64RegCacheFPU::Arm64RegCacheFPU(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::JitOptions *jo) : mips_(mips), vr(mr + 32), js_(js), jo_(jo), initialReady(false) {
numARMFpuReg_ = 32;
}
diff --git a/Core/MIPS/ARM64/Arm64RegCacheFPU.h b/Core/MIPS/ARM64/Arm64RegCacheFPU.h
index 7ba3dd01de..49bf37356e 100644
--- a/Core/MIPS/ARM64/Arm64RegCacheFPU.h
+++ b/Core/MIPS/ARM64/Arm64RegCacheFPU.h
@@ -77,13 +77,13 @@ struct FPURegMIPS {
};
namespace MIPSComp {
- struct Arm64JitOptions;
+ struct JitOptions;
struct JitState;
}
class Arm64RegCacheFPU {
public:
- Arm64RegCacheFPU(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::Arm64JitOptions *jo);
+ Arm64RegCacheFPU(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::JitOptions *jo);
~Arm64RegCacheFPU() {}
void Init(Arm64Gen::ARM64XEmitter *emitter, Arm64Gen::ARM64FloatEmitter *fp);
@@ -159,7 +159,7 @@ private:
Arm64Gen::ARM64XEmitter *emit_;
Arm64Gen::ARM64FloatEmitter *fp_;
MIPSComp::JitState *js_;
- MIPSComp::Arm64JitOptions *jo_;
+ MIPSComp::JitOptions *jo_;
int numARMFpuReg_;
int qTime_;
diff --git a/Core/MIPS/JitCommon/JitState.cpp b/Core/MIPS/JitCommon/JitState.cpp
new file mode 100644
index 0000000000..a679df0676
--- /dev/null
+++ b/Core/MIPS/JitCommon/JitState.cpp
@@ -0,0 +1,49 @@
+// Copyright (c) 2013- PPSSPP Project.
+
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, version 2.0 or later versions.
+
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License 2.0 for more details.
+
+// A copy of the GPL 2.0 should have been included with the program.
+// If not, see http://www.gnu.org/licenses/
+
+// Official git repository and contact information can be found at
+// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
+
+#include "Common/CPUDetect.h"
+#include "Core/MIPS/JitCommon/JitState.h"
+
+namespace MIPSComp {
+ JitOptions::JitOptions() {
+ // x86
+ enableVFPUSIMD = true;
+ // Set by Asm if needed.
+ reserveR15ForAsm = false;
+
+ // ARM/ARM64
+ useBackJump = false;
+ useForwardJump = false;
+ cachePointers = true;
+
+ // ARM only
+ downcountInRegister = true;
+ useNEONVFPU = false; // true
+ if (!cpu_info.bNEON)
+ useNEONVFPU = false;
+
+ //ARM64
+ useASIMDVFPU = false; // true
+
+ // Common
+ enableBlocklink = true;
+ immBranches = false;
+ continueBranches = false;
+ continueJumps = false;
+ continueMaxInstructions = 300;
+ }
+}
diff --git a/Core/MIPS/JitCommon/JitState.h b/Core/MIPS/JitCommon/JitState.h
index 0bb7007a6e..a296630a59 100644
--- a/Core/MIPS/JitCommon/JitState.h
+++ b/Core/MIPS/JitCommon/JitState.h
@@ -175,4 +175,29 @@ namespace MIPSComp {
}
}
};
+
+ struct JitOptions {
+ JitOptions();
+
+ // x86
+ bool enableVFPUSIMD;
+ bool reserveR15ForAsm;
+
+ // ARM/ARM64
+ bool useBackJump;
+ bool useForwardJump;
+ bool cachePointers;
+ // ARM only
+ bool useNEONVFPU;
+ bool downcountInRegister;
+ // ARM64 only
+ bool useASIMDVFPU;
+
+ // Common
+ bool enableBlocklink;
+ bool immBranches;
+ bool continueBranches;
+ bool continueJumps;
+ int continueMaxInstructions;
+ };
}
diff --git a/Core/MIPS/x86/Jit.cpp b/Core/MIPS/x86/Jit.cpp
index 886a9e54e0..b4283822dc 100644
--- a/Core/MIPS/x86/Jit.cpp
+++ b/Core/MIPS/x86/Jit.cpp
@@ -114,18 +114,6 @@ static void JitLogMiss(MIPSOpcode op)
func(op);
}
-JitOptions::JitOptions()
-{
- enableBlocklink = true;
- immBranches = false;
- continueBranches = false;
- continueJumps = false;
- continueMaxInstructions = 300;
- enableVFPUSIMD = true;
- // Set by Asm if needed.
- reserveR15ForAsm = false;
-}
-
#ifdef _MSC_VER
// JitBlockCache doesn't use this, just stores it.
#pragma warning(disable:4355)
diff --git a/Core/MIPS/x86/Jit.h b/Core/MIPS/x86/Jit.h
index cbafdb57cf..7d1ed8448a 100644
--- a/Core/MIPS/x86/Jit.h
+++ b/Core/MIPS/x86/Jit.h
@@ -41,19 +41,6 @@ namespace MIPSComp
// This is called when Jit hits a breakpoint. Returns 1 when hit.
u32 JitBreakpoint();
-struct JitOptions
-{
- JitOptions();
-
- bool enableBlocklink;
- bool immBranches;
- bool continueBranches;
- bool continueJumps;
- int continueMaxInstructions;
- bool enableVFPUSIMD;
- bool reserveR15ForAsm;
-};
-
// TODO: Hmm, humongous.
struct RegCacheState {
GPRRegCacheState gpr;
diff --git a/android/jni/Android.mk b/android/jni/Android.mk
index 1be24d8776..c209bba91a 100644
--- a/android/jni/Android.mk
+++ b/android/jni/Android.mk
@@ -314,6 +314,7 @@ EXEC_AND_LIB_FILES := \
$(SRC)/Core/FileSystems/tlzrc.cpp \
$(SRC)/Core/MIPS/JitCommon/JitCommon.cpp \
$(SRC)/Core/MIPS/JitCommon/JitBlockCache.cpp \
+ $(SRC)/Core/MIPS/JitCommon/JitState.cpp \
$(SRC)/Core/Util/AudioFormat.cpp \
$(SRC)/Core/Util/GameManager.cpp \
$(SRC)/Core/Util/BlockAllocator.cpp \
diff --git a/unittest/TestArmEmitter.cpp b/unittest/TestArmEmitter.cpp
index ea8a979e77..27da590dd2 100644
--- a/unittest/TestArmEmitter.cpp
+++ b/unittest/TestArmEmitter.cpp
@@ -199,7 +199,7 @@ bool TestArmEmitter() {
MIPSState mips;
MIPSComp::JitState js;
- MIPSComp::ArmJitOptions jo;
+ MIPSComp::JitOptions jo;
ArmRegCacheFPU fpr(&mips, &js, &jo);
fpr.SetEmitter(&emitter);
int C000 = GetColumnName(0, M_4x4, 0, 0);