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Make vertexFullAlpha-in-register work the same as on ARM.
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a164f77f47
commit
c9aa3479a4
1 changed files with 14 additions and 13 deletions
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@ -203,15 +203,10 @@ JittedVertexDecoder VertexDecoderJitCache::Compile(const VertexDecoder &dec, int
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MOVUPS(MDisp(ESP, 80), XMM9);
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MOVUPS(MDisp(ESP, 80), XMM9);
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#endif
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#endif
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// Initialize alpha reg if possible. TODO: Only do if color values with alpha are used.
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// Initialize alpha reg.
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#if PPSSPP_ARCH(AMD64)
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if (dec.col) {
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if (RipAccessible(&gstate_c.vertexFullAlpha)) {
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MOV(32, R(alphaReg), Imm32(1));
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MOV(8, R(alphaReg), M(&gstate_c.vertexFullAlpha)); // rip accessible
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} else {
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MOV(PTRBITS, R(tempReg1), ImmPtr(&gstate_c.vertexFullAlpha));
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MOV(8, R(alphaReg), MatR(tempReg1));
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}
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}
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#endif
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bool prescaleStep = false;
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bool prescaleStep = false;
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// Look for prescaled texcoord steps
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// Look for prescaled texcoord steps
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@ -286,11 +281,16 @@ JittedVertexDecoder VertexDecoderJitCache::Compile(const VertexDecoder &dec, int
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// Writeback alpha reg
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// Writeback alpha reg
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#if PPSSPP_ARCH(AMD64)
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#if PPSSPP_ARCH(AMD64)
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if (RipAccessible(&gstate_c.vertexFullAlpha)) {
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if (dec.col) {
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MOV(8, M(&gstate_c.vertexFullAlpha), R(alphaReg)); // rip accessible
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CMP(32, R(alphaReg), Imm32(1));
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} else {
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FixupBranch alphaJump = J_CC(CC_NE, false);
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MOV(PTRBITS, R(tempReg1), ImmPtr(&gstate_c.vertexFullAlpha));
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if (RipAccessible(&gstate_c.vertexFullAlpha)) {
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MOV(8, MatR(tempReg1), R(alphaReg));
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MOV(8, M(&gstate_c.vertexFullAlpha), Imm8(0)); // rip accessible
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} else {
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MOV(PTRBITS, R(tempReg1), ImmPtr(&gstate_c.vertexFullAlpha));
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MOV(8, MatR(tempReg1), Imm8(0)); // rip accessible
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}
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SetJumpTarget(alphaJump);
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}
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}
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#endif
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#endif
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@ -954,6 +954,7 @@ void VertexDecoderJitCache::Jit_Color8888() {
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CMP(32, R(tempReg1), Imm32(0xFF000000));
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CMP(32, R(tempReg1), Imm32(0xFF000000));
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FixupBranch skip = J_CC(CC_AE, false);
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FixupBranch skip = J_CC(CC_AE, false);
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#if PPSSPP_ARCH(AMD64)
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#if PPSSPP_ARCH(AMD64)
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// Would like to use CMOV or SetCC but CMOV doesn't take immediates and SetCC isn't right. So...
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XOR(32, R(alphaReg), R(alphaReg));
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XOR(32, R(alphaReg), R(alphaReg));
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#else
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#else
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if (RipAccessible(&gstate_c.vertexFullAlpha)) {
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if (RipAccessible(&gstate_c.vertexFullAlpha)) {
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