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https://github.com/hrydgard/ppsspp.git
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samplerjit: Better vectorize UV linear calc.
Gives about 1-2% when mips are used.
This commit is contained in:
Unknown W. Brackets
parent
733046962f
commit
c1e657ed47
5 changed files with 124 additions and 135 deletions
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@ -1920,8 +1920,30 @@ void XEmitter::PINSRW(X64Reg dest, OpArg arg, u8 subreg) {WriteSSEOp(0x66, 0x
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void XEmitter::PEXTRB(OpArg dest, X64Reg arg, u8 subreg) {WriteSSE41Op(0x66, 0x3A14, arg, dest, 1); Write8(subreg);}
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void XEmitter::PEXTRW(OpArg dest, X64Reg arg, u8 subreg) {WriteSSE41Op(0x66, 0x3A15, arg, dest, 1); Write8(subreg);}
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void XEmitter::PEXTRD(OpArg dest, X64Reg arg, u8 subreg) {WriteSSE41Op(0x66, 0x3A16, arg, dest, 1); Write8(subreg);}
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void XEmitter::PEXTRQ(OpArg dest, X64Reg arg, u8 subreg) {
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_assert_msg_(cpu_info.bSSE4_1, "Trying to use SSE4.1 on a system that doesn't support it.");
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Write8(0x66);
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dest.operandReg = arg;
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dest.WriteRex(this, 64, 0);
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Write8(0x0F);
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Write8(0x3A);
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Write8(0x16);
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dest.WriteRest(this, 1);
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Write8(subreg);
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}
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void XEmitter::PINSRB(X64Reg dest, OpArg arg, u8 subreg) {WriteSSE41Op(0x66, 0x3A20, dest, arg, 1); Write8(subreg);}
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void XEmitter::PINSRD(X64Reg dest, OpArg arg, u8 subreg) {WriteSSE41Op(0x66, 0x3A22, dest, arg, 1); Write8(subreg);}
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void XEmitter::PINSRQ(X64Reg dest, OpArg arg, u8 subreg) {
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_assert_msg_(cpu_info.bSSE4_1, "Trying to use SSE4.1 on a system that doesn't support it.");
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Write8(0x66);
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arg.operandReg = dest;
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arg.WriteRex(this, 64, 0);
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Write8(0x0F);
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Write8(0x3A);
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Write8(0x22);
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arg.WriteRest(this, 1);
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Write8(subreg);
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}
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void XEmitter::PMADDWD(X64Reg dest, OpArg arg) {WriteSSEOp(0x66, 0xF5, dest, arg); }
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void XEmitter::PMADDUBSW(X64Reg dest, OpArg arg) {WriteSSSE3Op(0x66, 0x3804, dest, arg);}
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@ -817,8 +817,10 @@ public:
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void PEXTRB(OpArg dest, X64Reg arg, u8 subreg);
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void PEXTRW(OpArg dest, X64Reg arg, u8 subreg);
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void PEXTRD(OpArg dest, X64Reg arg, u8 subreg);
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void PEXTRQ(OpArg dest, X64Reg arg, u8 subreg);
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void PINSRB(X64Reg dest, OpArg arg, u8 subreg);
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void PINSRD(X64Reg dest, OpArg arg, u8 subreg);
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void PINSRQ(X64Reg dest, OpArg arg, u8 subreg);
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void PMADDWD(X64Reg dest, OpArg arg);
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void PMADDUBSW(X64Reg dest, OpArg arg);
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@ -105,7 +105,7 @@ void SamplerJitCache::Clear() {
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const10Low_ = nullptr;
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const10All8_ = nullptr;
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constWidth256f_ = nullptr;
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constWidthHeight256f_ = nullptr;
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constHeight256f_ = nullptr;
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constWidthMinus1i_ = nullptr;
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constHeightMinus1i_ = nullptr;
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@ -104,7 +104,7 @@ private:
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int stackFracUV1Offset_ = 0;
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#endif
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const u8 *constWidth256f_ = nullptr;
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const u8 *constWidthHeight256f_ = nullptr;
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const u8 *constHeight256f_ = nullptr;
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const u8 *constWidthMinus1i_ = nullptr;
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const u8 *constHeightMinus1i_ = nullptr;
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@ -871,14 +871,18 @@ void SamplerJitCache::WriteConstantPool(const SamplerID &id) {
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// These are unique to the sampler ID.
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if (!id.hasAnyMips) {
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float w256f = (1 << id.width0Shift) * 256;
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WriteDynamicConst4x32(constWidth256f_, *(uint32_t *)&w256f);
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float h256f = (1 << id.height0Shift) * 256;
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constWidthHeight256f_ = AlignCode16();
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Write32(*(uint32_t *)&w256f);
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Write32(*(uint32_t *)&h256f);
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Write32(*(uint32_t *)&w256f);
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Write32(*(uint32_t *)&h256f);
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WriteDynamicConst4x32(constHeight256f_, *(uint32_t *)&h256f);
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WriteDynamicConst4x32(constWidthMinus1i_, (1 << id.width0Shift) - 1);
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WriteDynamicConst4x32(constHeightMinus1i_, (1 << id.height0Shift) - 1);
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} else {
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constWidth256f_ = nullptr;
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constWidthHeight256f_ = nullptr;
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constHeight256f_ = nullptr;
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constWidthMinus1i_ = nullptr;
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constHeightMinus1i_ = nullptr;
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@ -2394,7 +2398,7 @@ bool SamplerJitCache::Jit_GetTexelCoords(const SamplerID &id) {
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X64Reg vReg = regCache_.Alloc(RegCache::GEN_ARG_V);
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X64Reg sReg = regCache_.Find(RegCache::VEC_ARG_S);
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X64Reg tReg = regCache_.Find(RegCache::VEC_ARG_T);
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if (constWidth256f_ == nullptr) {
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if (constWidthHeight256f_ == nullptr) {
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// We have to figure out levels and the proper width, ugh.
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X64Reg idReg = GetSamplerID();
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X64Reg tempReg = regCache_.Alloc(RegCache::GEN_TEMP0);
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@ -2458,7 +2462,7 @@ bool SamplerJitCache::Jit_GetTexelCoords(const SamplerID &id) {
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regCache_.Release(tempVecReg, RegCache::VEC_TEMP0);
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} else {
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// Multiply, then convert to integer...
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MULSS(sReg, M(constWidth256f_));
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MULSS(sReg, M(constWidthHeight256f_));
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MULSS(tReg, M(constHeight256f_));
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CVTTPS2DQ(sReg, R(sReg));
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CVTTPS2DQ(tReg, R(tReg));
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@ -2517,13 +2521,11 @@ bool SamplerJitCache::Jit_GetTexelCoordsQuad(const SamplerID &id) {
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X64Reg sReg = regCache_.Find(RegCache::VEC_ARG_S);
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X64Reg tReg = regCache_.Find(RegCache::VEC_ARG_T);
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// Start by multiplying with the width/height... which might be complex with mips.
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X64Reg width0VecReg = INVALID_REG;
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X64Reg height0VecReg = INVALID_REG;
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X64Reg width1VecReg = INVALID_REG;
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X64Reg height1VecReg = INVALID_REG;
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// We use this if there are mips later, to apply wrap/clamp.
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X64Reg sizesReg = INVALID_REG;
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if (constWidth256f_ == nullptr) {
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// Start by multiplying with the width/height... which might be complex with mips.
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if (id.hasAnyMips) {
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// We have to figure out levels and the proper width, ugh.
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X64Reg idReg = GetSamplerID();
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@ -2539,8 +2541,16 @@ bool SamplerJitCache::Jit_GetTexelCoordsQuad(const SamplerID &id) {
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}
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// This will load the current and next level's sizes, 16x4.
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X64Reg sizesReg = regCache_.Alloc(RegCache::VEC_TEMP5);
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MOVQ_xmm(sizesReg, MComplex(idReg, levelReg, SCALE_4, offsetof(SamplerID, cached.sizes[0].w)));
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sizesReg = regCache_.Alloc(RegCache::VEC_TEMP5);
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// We actually want this in 32-bit, though, so extend.
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if (cpu_info.bSSE4_1) {
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PMOVZXWD(sizesReg, MComplex(idReg, levelReg, SCALE_4, offsetof(SamplerID, cached.sizes[0].w)));
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} else {
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MOVQ_xmm(sizesReg, MComplex(idReg, levelReg, SCALE_4, offsetof(SamplerID, cached.sizes[0].w)));
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X64Reg zeroReg = GetZeroVec();
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PUNPCKLWD(sizesReg, R(zeroReg));
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regCache_.Unlock(zeroReg, RegCache::VEC_ZERO);
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}
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if (releaseLevelReg)
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regCache_.Release(levelReg, RegCache::GEN_ARG_LEVEL);
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@ -2548,75 +2558,31 @@ bool SamplerJitCache::Jit_GetTexelCoordsQuad(const SamplerID &id) {
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regCache_.Unlock(levelReg, RegCache::GEN_ARG_LEVEL);
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UnlockSamplerID(idReg);
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X64Reg tempVecReg = regCache_.Alloc(RegCache::VEC_TEMP0);
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auto loadSizeAndMul = [&](X64Reg dest, X64Reg size, bool isY, bool isLevel1) {
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// Grab the size and mask out 16 bits using walls.
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if (cpu_info.bSSE4_1) {
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int lane = (isY ? 1 : 0) + (isLevel1 ? 2 : 0);
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PMOVZXWD(size, R(sizesReg));
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PSHUFD(size, R(size), _MM_SHUFFLE(lane, lane, lane, lane));
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} else {
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if (size != sizesReg)
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MOVDQA(size, R(sizesReg));
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PSLLQ(size, 48 - (isY ? 16 : 0) - (isLevel1 ? 32 : 0));
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PSRLQ(size, 48);
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PSHUFD(size, R(size), _MM_SHUFFLE(0, 0, 0, 0));
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}
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// Now make a float version of sizesReg, times 256.
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X64Reg sizes256Reg = regCache_.Alloc(RegCache::VEC_TEMP0);
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PSLLD(sizes256Reg, sizesReg, 8);
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CVTDQ2PS(sizes256Reg, R(sizes256Reg));
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PSLLD(tempVecReg, size, 8);
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CVTDQ2PS(tempVecReg, R(tempVecReg));
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// And then multiply.
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MULPS(dest, R(tempVecReg));
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};
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// Next off, move S and T into a single reg, which will become U0 V0 U1 V1.
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UNPCKLPS(sReg, R(tReg));
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SHUFPS(sReg, R(sReg), _MM_SHUFFLE(1, 0, 1, 0));
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// And multiply by the sizes, all lined up already.
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MULPS(sReg, R(sizes256Reg));
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regCache_.Release(sizes256Reg, RegCache::VEC_TEMP0);
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// Copy out S and T so we can multiply.
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X64Reg u1Reg = regCache_.Find(RegCache::VEC_U1);
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X64Reg v1Reg = regCache_.Find(RegCache::VEC_V1);
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MOVAPS(u1Reg, R(sReg));
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MOVAPS(v1Reg, R(tReg));
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// Load width and height for the given level, and multiply sReg/tReg meanwhile.
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width0VecReg = regCache_.Alloc(RegCache::VEC_TEMP2);
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loadSizeAndMul(sReg, width0VecReg, false, false);
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height0VecReg = regCache_.Alloc(RegCache::VEC_TEMP3);
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loadSizeAndMul(tReg, height0VecReg, true, false);
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// And same for the next level, but with u1Reg/v1Reg.
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width1VecReg = regCache_.Alloc(RegCache::VEC_TEMP4);
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loadSizeAndMul(u1Reg, width1VecReg, false, true);
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// We reuse this one we allocated above.
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height1VecReg = sizesReg;
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loadSizeAndMul(v1Reg, height1VecReg, true, true);
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regCache_.Unlock(u1Reg, RegCache::VEC_U1);
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regCache_.Unlock(v1Reg, RegCache::VEC_V1);
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// Now just subtract one. We use this later for clamp/wrap.
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MOVDQA(tempVecReg, M(constOnes32_));
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PSUBD(width0VecReg, R(tempVecReg));
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PSUBD(height0VecReg, R(tempVecReg));
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PSUBD(width1VecReg, R(tempVecReg));
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PSUBD(height1VecReg, R(tempVecReg));
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regCache_.Release(tempVecReg, RegCache::VEC_TEMP0);
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// For wrap/clamp purposes, we want width or height minus one. Do that now.
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PSUBD(sizesReg, M(constOnes32_));
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} else {
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// Easy mode.
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MULSS(sReg, M(constWidth256f_));
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MULSS(tReg, M(constHeight256f_));
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UNPCKLPS(sReg, R(tReg));
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MULPS(sReg, M(constWidthHeight256f_));
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}
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// And now, convert to integers for all later processing.
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CVTPS2DQ(sReg, R(sReg));
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CVTPS2DQ(tReg, R(tReg));
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if (regCache_.Has(RegCache::VEC_U1)) {
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X64Reg u1Reg = regCache_.Find(RegCache::VEC_U1);
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X64Reg v1Reg = regCache_.Find(RegCache::VEC_V1);
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CVTPS2DQ(u1Reg, R(u1Reg));
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CVTPS2DQ(v1Reg, R(v1Reg));
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regCache_.Unlock(u1Reg, RegCache::VEC_U1);
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regCache_.Unlock(v1Reg, RegCache::VEC_V1);
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}
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// Now adjust X and Y...
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// TODO: Could we cache this? Should only vary on offset, maybe?
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X64Reg xReg = regCache_.Find(RegCache::GEN_ARG_X);
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X64Reg yReg = regCache_.Find(RegCache::GEN_ARG_Y);
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NEG(32, R(xReg));
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@ -2629,19 +2595,9 @@ bool SamplerJitCache::Jit_GetTexelCoordsQuad(const SamplerID &id) {
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// Add them in. We do this in the SSE because we have more to do there...
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X64Reg tempXYReg = regCache_.Alloc(RegCache::VEC_TEMP0);
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MOVQ_xmm(tempXYReg, R(xReg));
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if (id.hasAnyMips)
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PSHUFD(tempXYReg, R(tempXYReg), _MM_SHUFFLE(1, 0, 1, 0));
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PADDD(sReg, R(tempXYReg));
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if (regCache_.Has(RegCache::VEC_U1)) {
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X64Reg u1Reg = regCache_.Find(RegCache::VEC_U1);
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PADDD(u1Reg, R(tempXYReg));
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regCache_.Unlock(u1Reg, RegCache::VEC_U1);
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}
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PSHUFD(tempXYReg, R(tempXYReg), _MM_SHUFFLE(1, 1, 1, 1));
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PADDD(tReg, R(tempXYReg));
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if (regCache_.Has(RegCache::VEC_V1)) {
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X64Reg v1Reg = regCache_.Find(RegCache::VEC_V1);
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PADDD(v1Reg, R(tempXYReg));
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regCache_.Unlock(v1Reg, RegCache::VEC_V1);
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}
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regCache_.Release(tempXYReg, RegCache::VEC_TEMP0);
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regCache_.Unlock(xReg, RegCache::GEN_ARG_X);
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@ -2652,54 +2608,54 @@ bool SamplerJitCache::Jit_GetTexelCoordsQuad(const SamplerID &id) {
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// We do want the fraction, though, so extract that.
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X64Reg fracUReg = regCache_.Find(RegCache::GEN_ARG_FRAC_U);
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X64Reg fracVReg = regCache_.Find(RegCache::GEN_ARG_FRAC_V);
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if (regCache_.Has(RegCache::VEC_U1)) {
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// Start with the next level so we end with current in the regs.
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X64Reg u1Reg = regCache_.Find(RegCache::VEC_U1);
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X64Reg v1Reg = regCache_.Find(RegCache::VEC_V1);
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MOVD_xmm(R(fracUReg), u1Reg);
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MOVD_xmm(R(fracVReg), v1Reg);
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SHR(32, R(fracUReg), Imm8(4));
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AND(32, R(fracUReg), Imm8(0x0F));
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SHR(32, R(fracVReg), Imm8(4));
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AND(32, R(fracVReg), Imm8(0x0F));
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regCache_.Unlock(u1Reg, RegCache::VEC_U1);
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regCache_.Unlock(v1Reg, RegCache::VEC_V1);
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// Store them on the stack for now.
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MOV(32, MDisp(RSP, stackArgPos_ + stackFracUV1Offset_), R(fracUReg));
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MOV(32, MDisp(RSP, stackArgPos_ + stackFracUV1Offset_ + 4), R(fracVReg));
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X64Reg fracExtractReg = regCache_.Alloc(RegCache::VEC_TEMP0);
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// We only want the four bits after the first four, though.
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PSLLD(fracExtractReg, sReg, 24);
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PSRLD(fracExtractReg, 28);
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// Okay, grab the regs.
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if (cpu_info.bSSE4_1) {
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MOVD_xmm(R(fracUReg), fracExtractReg);
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PEXTRD(R(fracVReg), fracExtractReg, 1);
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} else {
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MOVD_xmm(R(fracUReg), fracExtractReg);
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PSRLDQ(fracExtractReg, 4);
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MOVD_xmm(R(fracVReg), fracExtractReg);
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}
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MOVD_xmm(R(fracUReg), sReg);
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MOVD_xmm(R(fracVReg), tReg);
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SHR(32, R(fracUReg), Imm8(4));
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AND(32, R(fracUReg), Imm8(0x0F));
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SHR(32, R(fracVReg), Imm8(4));
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AND(32, R(fracVReg), Imm8(0x0F));
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// And store frac U1/V1 on the stack, if we have mips.
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if (id.hasAnyMips) {
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if (cpu_info.bSSE4_1) {
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// They're next to each other, so one extract is enough.
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PEXTRQ(MDisp(RSP, stackArgPos_ + stackFracUV1Offset_), fracExtractReg, 1);
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} else {
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// We already shifted 4 for fracVReg, shift again and store.
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PSRLDQ(fracExtractReg, 4);
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MOVQ_xmm(MDisp(RSP, stackArgPos_ + stackFracUV1Offset_), fracExtractReg);
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}
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}
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regCache_.Release(fracExtractReg, RegCache::VEC_TEMP0);
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regCache_.Unlock(fracUReg, RegCache::GEN_ARG_FRAC_U);
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regCache_.Unlock(fracVReg, RegCache::GEN_ARG_FRAC_V);
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// Get rid of the fractional bits, and spread out.
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PSHUFD(sReg, R(sReg), _MM_SHUFFLE(0, 0, 0, 0));
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PSHUFD(tReg, R(tReg), _MM_SHUFFLE(0, 0, 0, 0));
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// With those extracted, we can now get rid of the fractional bits.
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PSRAD(sReg, 8);
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PSRAD(tReg, 8);
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// Add U/V values for the next coords.
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PADDD(sReg, M(constUNext_));
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PADDD(tReg, M(constVNext_));
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if (regCache_.Has(RegCache::VEC_U1)) {
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// Now it's time to separate the lanes into separate registers and add next UV offsets.
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if (id.hasAnyMips) {
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X64Reg u1Reg = regCache_.Find(RegCache::VEC_U1);
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X64Reg v1Reg = regCache_.Find(RegCache::VEC_V1);
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PSHUFD(u1Reg, R(u1Reg), _MM_SHUFFLE(0, 0, 0, 0));
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PSHUFD(v1Reg, R(v1Reg), _MM_SHUFFLE(0, 0, 0, 0));
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PSRAD(u1Reg, 8);
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PSRAD(v1Reg, 8);
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PSHUFD(u1Reg, R(sReg), _MM_SHUFFLE(2, 2, 2, 2));
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PSHUFD(v1Reg, R(sReg), _MM_SHUFFLE(3, 3, 3, 3));
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PADDD(u1Reg, M(constUNext_));
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PADDD(v1Reg, M(constVNext_));
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regCache_.Unlock(u1Reg, RegCache::VEC_U1);
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regCache_.Unlock(v1Reg, RegCache::VEC_V1);
|
||||
}
|
||||
|
||||
PSHUFD(tReg, R(sReg), _MM_SHUFFLE(1, 1, 1, 1));
|
||||
PSHUFD(sReg, R(sReg), _MM_SHUFFLE(0, 0, 0, 0));
|
||||
PADDD(tReg, M(constVNext_));
|
||||
PADDD(sReg, M(constUNext_));
|
||||
|
||||
X64Reg temp0ClampReg = regCache_.Alloc(RegCache::VEC_TEMP0);
|
||||
bool temp0ClampZero = false;
|
||||
|
||||
|
|
@ -2724,8 +2680,12 @@ bool SamplerJitCache::Jit_GetTexelCoordsQuad(const SamplerID &id) {
|
|||
PANDN(temp0ClampReg, R(stReg));
|
||||
|
||||
// Now make a mask where bound is greater than the ST value in temp0ClampReg.
|
||||
MOVDQA(stReg, bound);
|
||||
PCMPGTD(stReg, R(temp0ClampReg));
|
||||
if (cpu_info.bAVX && bound.IsSimpleReg()) {
|
||||
VPCMPGTD(128, stReg, bound.GetSimpleReg(), R(temp0ClampReg));
|
||||
} else {
|
||||
MOVDQA(stReg, bound);
|
||||
PCMPGTD(stReg, R(temp0ClampReg));
|
||||
}
|
||||
// Throw away the values that are greater in our temp0ClampReg in progress result.
|
||||
PAND(temp0ClampReg, R(stReg));
|
||||
|
||||
|
|
@ -2736,26 +2696,31 @@ bool SamplerJitCache::Jit_GetTexelCoordsQuad(const SamplerID &id) {
|
|||
}
|
||||
};
|
||||
|
||||
doClamp(id.clampS, sReg, width0VecReg == INVALID_REG ? M(constWidthMinus1i_) : R(width0VecReg));
|
||||
doClamp(id.clampT, tReg, height0VecReg == INVALID_REG ? M(constHeightMinus1i_) : R(height0VecReg));
|
||||
if (width1VecReg != INVALID_REG) {
|
||||
if (id.hasAnyMips) {
|
||||
// We'll spread sizes out into a temp.
|
||||
X64Reg spreadSizeReg = regCache_.Alloc(RegCache::VEC_TEMP1);
|
||||
|
||||
PSHUFD(spreadSizeReg, R(sizesReg), _MM_SHUFFLE(0, 0, 0, 0));
|
||||
doClamp(id.clampS, sReg, R(spreadSizeReg));
|
||||
PSHUFD(spreadSizeReg, R(sizesReg), _MM_SHUFFLE(1, 1, 1, 1));
|
||||
doClamp(id.clampT, tReg, R(spreadSizeReg));
|
||||
X64Reg u1Reg = regCache_.Find(RegCache::VEC_U1);
|
||||
X64Reg v1Reg = regCache_.Find(RegCache::VEC_V1);
|
||||
doClamp(id.clampS, u1Reg, R(width1VecReg));
|
||||
doClamp(id.clampT, v1Reg, R(height1VecReg));
|
||||
PSHUFD(spreadSizeReg, R(sizesReg), _MM_SHUFFLE(2, 2, 2, 2));
|
||||
doClamp(id.clampS, u1Reg, R(spreadSizeReg));
|
||||
PSHUFD(spreadSizeReg, R(sizesReg), _MM_SHUFFLE(3, 3, 3, 3));
|
||||
doClamp(id.clampT, v1Reg, R(spreadSizeReg));
|
||||
regCache_.Unlock(u1Reg, RegCache::VEC_U1);
|
||||
regCache_.Unlock(v1Reg, RegCache::VEC_V1);
|
||||
|
||||
regCache_.Release(spreadSizeReg, RegCache::VEC_TEMP1);
|
||||
} else {
|
||||
doClamp(id.clampS, sReg, M(constWidthMinus1i_));
|
||||
doClamp(id.clampT, tReg, M(constHeightMinus1i_));
|
||||
}
|
||||
|
||||
if (width0VecReg != INVALID_REG)
|
||||
regCache_.Release(width0VecReg, RegCache::VEC_TEMP2);
|
||||
if (height0VecReg != INVALID_REG)
|
||||
regCache_.Release(height0VecReg, RegCache::VEC_TEMP3);
|
||||
if (width1VecReg != INVALID_REG)
|
||||
regCache_.Release(width1VecReg, RegCache::VEC_TEMP4);
|
||||
if (height1VecReg != INVALID_REG)
|
||||
regCache_.Release(height1VecReg, RegCache::VEC_TEMP5);
|
||||
|
||||
if (sizesReg != INVALID_REG)
|
||||
regCache_.Release(sizesReg, RegCache::VEC_TEMP5);
|
||||
regCache_.Release(temp0ClampReg, RegCache::VEC_TEMP0);
|
||||
|
||||
regCache_.Unlock(sReg, RegCache::VEC_ARG_S);
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue