diff --git a/Core/MIPS/IR/IRCompBranch.cpp b/Core/MIPS/IR/IRCompBranch.cpp index 3a7affbd99..bb08883cc1 100644 --- a/Core/MIPS/IR/IRCompBranch.cpp +++ b/Core/MIPS/IR/IRCompBranch.cpp @@ -92,7 +92,7 @@ void IRFrontend::BranchRSRTComp(MIPSOpcode op, IRComparison cc, bool likely) { CompileDelaySlot(); int dcAmount = js.downcountAmount; - ir.Write(IROp::Downcount, 0, dcAmount & 0xFF, dcAmount >> 8); + ir.Write(IROp::Downcount, 0, ir.AddConstant(dcAmount)); js.downcountAmount = 0; FlushAll(); @@ -133,7 +133,7 @@ void IRFrontend::BranchRSZeroComp(MIPSOpcode op, IRComparison cc, bool andLink, CompileDelaySlot(); int dcAmount = js.downcountAmount; - ir.Write(IROp::Downcount, 0, dcAmount & 0xFF, dcAmount >> 8); + ir.Write(IROp::Downcount, 0, ir.AddConstant(dcAmount)); js.downcountAmount = 0; FlushAll(); @@ -200,7 +200,7 @@ void IRFrontend::BranchFPFlag(MIPSOpcode op, IRComparison cc, bool likely) { CompileDelaySlot(); int dcAmount = js.downcountAmount; - ir.Write(IROp::Downcount, 0, dcAmount & 0xFF, dcAmount >> 8); + ir.Write(IROp::Downcount, 0, ir.AddConstant(dcAmount)); js.downcountAmount = 0; FlushAll(); @@ -249,7 +249,7 @@ void IRFrontend::BranchVFPUFlag(MIPSOpcode op, IRComparison cc, bool likely) { CompileDelaySlot(); int dcAmount = js.downcountAmount; - ir.Write(IROp::Downcount, 0, dcAmount & 0xFF, dcAmount >> 8); + ir.Write(IROp::Downcount, 0, ir.AddConstant(dcAmount)); js.downcountAmount = 0; if (delaySlotIsBranch && (signed short)(delaySlotOp & 0xFFFF) != (signed short)(op & 0xFFFF) - 1) @@ -320,7 +320,7 @@ void IRFrontend::Comp_Jump(MIPSOpcode op) { } int dcAmount = js.downcountAmount; - ir.Write(IROp::Downcount, 0, dcAmount & 0xFF, dcAmount >> 8); + ir.Write(IROp::Downcount, 0, ir.AddConstant(dcAmount)); js.downcountAmount = 0; FlushAll(); @@ -384,7 +384,7 @@ void IRFrontend::Comp_JumpReg(MIPSOpcode op) { } int dcAmount = js.downcountAmount; - ir.Write(IROp::Downcount, 0, dcAmount & 0xFF, dcAmount >> 8); + ir.Write(IROp::Downcount, 0, ir.AddConstant(dcAmount)); js.downcountAmount = 0; ir.Write(IROp::ExitToReg, 0, destReg, 0); @@ -397,7 +397,7 @@ void IRFrontend::Comp_JumpReg(MIPSOpcode op) { void IRFrontend::Comp_Syscall(MIPSOpcode op) { // Note: If we're in a delay slot, this is off by one compared to the interpreter. int dcAmount = js.downcountAmount + (js.inDelaySlot ? -1 : 0); - ir.Write(IROp::Downcount, 0, dcAmount & 0xFF, dcAmount >> 8); + ir.Write(IROp::Downcount, 0, ir.AddConstant(dcAmount)); js.downcountAmount = 0; // If not in a delay slot, we need to update PC. diff --git a/Core/MIPS/IR/IRFrontend.cpp b/Core/MIPS/IR/IRFrontend.cpp index bad7927b45..8174fa17f2 100644 --- a/Core/MIPS/IR/IRFrontend.cpp +++ b/Core/MIPS/IR/IRFrontend.cpp @@ -162,7 +162,7 @@ void IRFrontend::Comp_ReplacementFunc(MIPSOpcode op) { MIPSCompileOp(Memory::Read_Instruction(GetCompilerPC(), true), this); } else { ApplyRoundingMode(); - ir.Write(IROp::Downcount, 0, js.downcountAmount & 0xFF, js.downcountAmount >> 8); + ir.Write(IROp::Downcount, 0, ir.AddConstant(js.downcountAmount)); ir.Write(IROp::ExitToReg, 0, MIPS_REG_RA, 0); js.compiling = false; } @@ -319,7 +319,7 @@ void IRFrontend::CheckBreakpoint(u32 addr) { // TODO: In likely branches, downcount will be incorrect. int downcountOffset = js.inDelaySlot && js.downcountAmount >= 2 ? -2 : 0; int downcountAmount = js.downcountAmount + downcountOffset; - ir.Write(IROp::Downcount, 0, downcountAmount & 0xFF, downcountAmount >> 8); + ir.Write(IROp::Downcount, 0, ir.AddConstant(downcountAmount)); // Note that this means downcount can't be metadata on the block. js.downcountAmount = -downcountOffset; ir.Write(IROp::Breakpoint); @@ -342,7 +342,7 @@ void IRFrontend::CheckMemoryBreakpoint(int rs, int offset) { downcountOffset = 0; } int downcountAmount = js.downcountAmount + downcountOffset; - ir.Write(IROp::Downcount, 0, downcountAmount & 0xFF, downcountAmount >> 8); + ir.Write(IROp::Downcount, 0, ir.AddConstant(downcountAmount)); // Note that this means downcount can't be metadata on the block. js.downcountAmount = -downcountOffset; ir.Write(IROp::MemoryCheck, 0, rs, ir.AddConstant(offset)); diff --git a/Core/MIPS/IR/IRInst.cpp b/Core/MIPS/IR/IRInst.cpp index fbdc25b5dd..2bd21d3fc3 100644 --- a/Core/MIPS/IR/IRInst.cpp +++ b/Core/MIPS/IR/IRInst.cpp @@ -141,7 +141,7 @@ static const IRMeta irMeta[] = { { IROp::Vec2Pack31To16, "Vec2Pack31To16", "2V" }, { IROp::Interpret, "Interpret", "_C" }, - { IROp::Downcount, "Downcount", "_II" }, + { IROp::Downcount, "Downcount", "_C" }, { IROp::ExitToPC, "ExitToPC", "", IRFLAG_EXIT }, { IROp::ExitToConst, "Exit", "C", IRFLAG_EXIT }, { IROp::ExitToConstIfEq, "ExitIfEq", "CGG", IRFLAG_EXIT }, diff --git a/Core/MIPS/IR/IRInterpreter.cpp b/Core/MIPS/IR/IRInterpreter.cpp index f1e8c348c8..8de1fea2ec 100644 --- a/Core/MIPS/IR/IRInterpreter.cpp +++ b/Core/MIPS/IR/IRInterpreter.cpp @@ -762,7 +762,7 @@ u32 IRInterpret(MIPSState *mips, const IRInst *inst, int count) { break; case IROp::Downcount: - mips->downcount -= (inst->src1) | ((inst->src2) << 8); + mips->downcount -= inst->constant; break; case IROp::SetPC: