diff --git a/Core/MIPS/RiscV/RiscVRegCache.cpp b/Core/MIPS/RiscV/RiscVRegCache.cpp
index 6ddf909977..6c966dabe7 100644
--- a/Core/MIPS/RiscV/RiscVRegCache.cpp
+++ b/Core/MIPS/RiscV/RiscVRegCache.cpp
@@ -958,14 +958,6 @@ bool RiscVRegCache::IsImm(IRRegIndex r) const {
 		return mr[r].loc == MIPSLoc::IMM || mr[r].loc == MIPSLoc::RVREG_IMM;
 }
 
-bool RiscVRegCache::IsPureImm(IRRegIndex r) const {
-	_dbg_assert_(IsValidReg(r));
-	if (r == MIPS_REG_ZERO)
-		return true;
-	else
-		return mr[r].loc == MIPSLoc::IMM;
-}
-
 u64 RiscVRegCache::GetImm(IRRegIndex r) const {
 	_dbg_assert_(IsValidReg(r));
 	if (r == MIPS_REG_ZERO)
diff --git a/Core/MIPS/RiscV/RiscVRegCache.h b/Core/MIPS/RiscV/RiscVRegCache.h
index 3984748318..b3a8835152 100644
--- a/Core/MIPS/RiscV/RiscVRegCache.h
+++ b/Core/MIPS/RiscV/RiscVRegCache.h
@@ -116,10 +116,7 @@ public:
 
 	void SetImm(IRRegIndex reg, u64 immVal);
 	bool IsImm(IRRegIndex reg) const;
-	bool IsPureImm(IRRegIndex reg) const;
 	u64 GetImm(IRRegIndex reg) const;
-	// Optimally set a register to an imm value (possibly using another register.)
-	void SetRegImm(RiscVGen::RiscVReg reg, u64 imm);
 
 	// May fail and return INVALID_REG if it needs flushing.
 	RiscVGen::RiscVReg TryMapTempImm(IRRegIndex);
@@ -144,7 +141,6 @@ public:
 	void MapDirtyInIn(IRRegIndex rd, IRRegIndex rs, IRRegIndex rt, RiscVJitConstants::MapType type = RiscVJitConstants::MapType::AVOID_LOAD);
 	void MapDirtyDirtyIn(IRRegIndex rd1, IRRegIndex rd2, IRRegIndex rs, RiscVJitConstants::MapType type = RiscVJitConstants::MapType::AVOID_LOAD);
 	void MapDirtyDirtyInIn(IRRegIndex rd1, IRRegIndex rd2, IRRegIndex rs, IRRegIndex rt, RiscVJitConstants::MapType type = RiscVJitConstants::MapType::AVOID_LOAD);
-	void FlushRiscVReg(RiscVGen::RiscVReg r);
 	void FlushBeforeCall();
 	void FlushAll();
 	void FlushR(IRRegIndex r);
@@ -171,6 +167,8 @@ private:
 	RiscVGen::RiscVReg AllocateReg();
 	RiscVGen::RiscVReg FindBestToSpill(bool unusedOnly, bool *clobbered);
 	RiscVGen::RiscVReg RiscVRegForFlush(IRRegIndex r);
+	void FlushRiscVReg(RiscVGen::RiscVReg r);
+	void SetRegImm(RiscVGen::RiscVReg reg, u64 imm);
 	void AddMemBase(RiscVGen::RiscVReg reg);
 	int GetMipsRegOffset(IRRegIndex r);