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armjit: Avoid flushing an imm in beq/bne/etc.

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We might be able to STMIA it instead.
This commit is contained in:
Unknown W. Brackets 2013-11-10 11:50:26 -08:00
parent 285ec1fad5
commit b30928036e
2 changed files with 24 additions and 19 deletions
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41
Core/MIPS/ARM/ArmCompBranch.cpp
View file

@ -71,33 +71,38 @@ void Jit::BranchRSRTComp(MIPSOpcode op, ArmGen::CCFlags cc, bool likely)
if (!likely && delaySlotIsNice) if (!likely && delaySlotIsNice)
CompileDelaySlot(DELAYSLOT_NICE); CompileDelaySlot(DELAYSLOT_NICE);
if (gpr.IsImm(rt) && gpr.GetImm(rt) == 0) // We might be able to flip the condition (EQ/NEQ are easy.)
{ const bool canFlip = cc == CC_EQ || cc == CC_NEQ;
Operand2 op2;
bool negated;
if (gpr.IsImm(rt) && TryMakeOperand2_AllowNegation(gpr.GetImm(rt), op2, &negated)) {
gpr.MapReg(rs); gpr.MapReg(rs);
CMP(gpr.R(rs), Operand2(0, TYPE_IMM)); if (!negated)
} CMP(gpr.R(rs), op2);
else if (gpr.IsImm(rs) && gpr.GetImm(rs) == 0 && (cc == CC_EQ || cc == CC_NEQ)) // only these are easily 'flippable' else
{ CMN(gpr.R(rs), op2);
gpr.MapReg(rt); } else {
CMP(gpr.R(rt), Operand2(0, TYPE_IMM)); if (gpr.IsImm(rs) && TryMakeOperand2_AllowNegation(gpr.GetImm(rs), op2, &negated) && canFlip) {
} gpr.MapReg(rt);
else if (!negated)
{ CMP(gpr.R(rt), op2);
gpr.MapInIn(rs, rt); else
CMP(gpr.R(rs), gpr.R(rt)); CMN(gpr.R(rt), op2);
} else {
gpr.MapInIn(rs, rt);
CMP(gpr.R(rs), gpr.R(rt));
}
} }
ArmGen::FixupBranch ptr; ArmGen::FixupBranch ptr;
if (!likely) if (!likely) {
{
if (!delaySlotIsNice) if (!delaySlotIsNice)
CompileDelaySlot(DELAYSLOT_SAFE_FLUSH); CompileDelaySlot(DELAYSLOT_SAFE_FLUSH);
else else
FlushAll(); FlushAll();
ptr = B_CC(cc); ptr = B_CC(cc);
} } else {
else
{
FlushAll(); FlushAll();
ptr = B_CC(cc); ptr = B_CC(cc);
CompileDelaySlot(DELAYSLOT_FLUSH); CompileDelaySlot(DELAYSLOT_FLUSH);

2
Core/MIPS/x86/CompBranch.cpp
View file

@ -187,7 +187,7 @@ void Jit::BranchRSRTComp(MIPSOpcode op, Gen::CCFlags cc, bool likely)
else else
{ {
gpr.MapReg(rs, true, false); gpr.MapReg(rs, true, false);
CMP(32, gpr.R(rs), rt == MIPS_REG_ZERO ? Imm32(0) : gpr.R(rt)); CMP(32, gpr.R(rs), gpr.R(rt));
} }
Gen::FixupBranch ptr; Gen::FixupBranch ptr;