From afcb5add51af3e7ab4e917095b955786dac44211 Mon Sep 17 00:00:00 2001 From: Henrik Rydgard Date: Sat, 27 Jul 2013 22:14:01 +0200 Subject: [PATCH] Minor code cleanup/reindent around ARM jit --- Core/MIPS/ARM/ArmCompFPU.cpp | 46 ++++++++++---------- Core/MIPS/ARM/ArmCompVFPU.cpp | 74 ++++++++++++++++----------------- Core/MIPS/JitCommon/JitCommon.h | 1 + Core/MIPS/MIPS.cpp | 47 +++++++++++++++++++++ Core/MIPS/MIPS.h | 2 + Core/MIPS/MIPSIntVFPU.cpp | 26 +----------- Core/MIPS/x86/CompVFPU.cpp | 40 ------------------ 7 files changed, 110 insertions(+), 126 deletions(-) diff --git a/Core/MIPS/ARM/ArmCompFPU.cpp b/Core/MIPS/ARM/ArmCompFPU.cpp index 3b7b8cef84..231a0f61b7 100644 --- a/Core/MIPS/ARM/ArmCompFPU.cpp +++ b/Core/MIPS/ARM/ArmCompFPU.cpp @@ -56,10 +56,10 @@ void Jit::Comp_FPU3op(u32 op) case 2: { //F(fd) = F(fs) * F(ft); //mul u32 nextOp = Memory::Read_Instruction(js.compilerPC + 4); // Optimise possible if destination is the same - if (fd == (int)((nextOp>>6) & 0x1F)) { + if (fd == ((nextOp>>6) & 0x1F)) { // VMUL + VNEG -> VNMUL if (!strcmp(MIPSGetName(nextOp), "neg.s")) { - if (fd == (int)((nextOp>>11) & 0x1F)) { + if (fd == ((nextOp>>11) & 0x1F)) { VNMUL(fpr.R(fd), fpr.R(fs), fpr.R(ft)); EatInstruction(nextOp); } @@ -106,15 +106,15 @@ void Jit::Comp_FPULS(u32 op) ADD(R0, R0, R11); } #ifdef __ARM_ARCH_7S__ - FixupBranch skip; - if (doCheck) { - skip = B_CC(CC_EQ); - } - VLDR(fpr.R(ft), R0, 0); - if (doCheck) { - SetJumpTarget(skip); - SetCC(CC_AL); - } + FixupBranch skip; + if (doCheck) { + skip = B_CC(CC_EQ); + } + VLDR(fpr.R(ft), R0, 0); + if (doCheck) { + SetJumpTarget(skip); + SetCC(CC_AL); + } #else VLDR(fpr.R(ft), R0, 0); if (doCheck) { @@ -142,15 +142,15 @@ void Jit::Comp_FPULS(u32 op) ADD(R0, R0, R11); } #ifdef __ARM_ARCH_7S__ - FixupBranch skip2; - if (doCheck) { - skip2 = B_CC(CC_EQ); - } - VSTR(fpr.R(ft), R0, 0); - if (doCheck) { - SetJumpTarget(skip2); - SetCC(CC_AL); - } + FixupBranch skip2; + if (doCheck) { + skip2 = B_CC(CC_EQ); + } + VSTR(fpr.R(ft), R0, 0); + if (doCheck) { + SetJumpTarget(skip2); + SetCC(CC_AL); + } #else VSTR(fpr.R(ft), R0, 0); if (doCheck) { @@ -169,8 +169,7 @@ void Jit::Comp_FPUComp(u32 op) { CONDITIONAL_DISABLE; int opc = op & 0xF; if (opc >= 8) opc -= 8; // alias - if (opc == 0)//f, sf (signalling false) - { + if (opc == 0) { // f, sf (signalling false) MOVI2R(R0, 0); STR(R0, CTXREG, offsetof(MIPSState, fpcond)); return; @@ -238,7 +237,6 @@ void Jit::Comp_FPU2op(u32 op) int fs = _FS; int fd = _FD; - // logBlocks = 1; switch (op & 0x3f) { @@ -314,7 +312,7 @@ void Jit::Comp_mxc1(u32 op) int fs = _FS; int rt = _RT; - switch((op >> 21) & 0x1f) + switch ((op >> 21) & 0x1f) { case 0: // R(rt) = FI(fs); break; //mfc1 // Let's just go through RAM for now. diff --git a/Core/MIPS/ARM/ArmCompVFPU.cpp b/Core/MIPS/ARM/ArmCompVFPU.cpp index b591f48eea..e64b33bab5 100644 --- a/Core/MIPS/ARM/ArmCompVFPU.cpp +++ b/Core/MIPS/ARM/ArmCompVFPU.cpp @@ -217,15 +217,15 @@ namespace MIPSComp ADD(R0, R0, R11); } #ifdef __ARM_ARCH_7S__ - FixupBranch skip; - if (doCheck) { - skip = B_CC(CC_EQ); - } - VLDR(fpr.V(vt), R0, 0); - if (doCheck) { - SetJumpTarget(skip); - SetCC(CC_AL); - } + FixupBranch skip; + if (doCheck) { + skip = B_CC(CC_EQ); + } + VLDR(fpr.V(vt), R0, 0); + if (doCheck) { + SetJumpTarget(skip); + SetCC(CC_AL); + } #else VLDR(fpr.V(vt), R0, 0); if (doCheck) { @@ -256,15 +256,15 @@ namespace MIPSComp ADD(R0, R0, R11); } #ifdef __ARM_ARCH_7S__ - FixupBranch skip; - if (doCheck) { - skip = B_CC(CC_EQ); - } - VSTR(fpr.V(vt), R0, 0); - if (doCheck) { - SetJumpTarget(skip); - SetCC(CC_AL); - } + FixupBranch skip; + if (doCheck) { + skip = B_CC(CC_EQ); + } + VSTR(fpr.V(vt), R0, 0); + if (doCheck) { + SetJumpTarget(skip); + SetCC(CC_AL); + } #else VSTR(fpr.V(vt), R0, 0); if (doCheck) { @@ -314,18 +314,18 @@ namespace MIPSComp } #ifdef __ARM_ARCH_7S__ - FixupBranch skip; - if (doCheck) { - skip = B_CC(CC_EQ); - } - + FixupBranch skip; + if (doCheck) { + skip = B_CC(CC_EQ); + } + for (int i = 0; i < 4; i++) VLDR(fpr.V(vregs[i]), R0, i * 4); - - if (doCheck) { - SetJumpTarget(skip); - SetCC(CC_AL); - } + + if (doCheck) { + SetJumpTarget(skip); + SetCC(CC_AL); + } #else for (int i = 0; i < 4; i++) VLDR(fpr.V(vregs[i]), R0, i * 4); @@ -364,18 +364,18 @@ namespace MIPSComp } #ifdef __ARM_ARCH_7S__ - FixupBranch skip; - if (doCheck) { - skip = B_CC(CC_EQ); - } - + FixupBranch skip; + if (doCheck) { + skip = B_CC(CC_EQ); + } + for (int i = 0; i < 4; i++) VSTR(fpr.V(vregs[i]), R0, i * 4); - if (doCheck) { - SetJumpTarget(skip); - SetCC(CC_AL); - } + if (doCheck) { + SetJumpTarget(skip); + SetCC(CC_AL); + } #else for (int i = 0; i < 4; i++) VSTR(fpr.V(vregs[i]), R0, i * 4); diff --git a/Core/MIPS/JitCommon/JitCommon.h b/Core/MIPS/JitCommon/JitCommon.h index bdc16a0825..52c1726bc4 100644 --- a/Core/MIPS/JitCommon/JitCommon.h +++ b/Core/MIPS/JitCommon/JitCommon.h @@ -42,4 +42,5 @@ namespace MIPSComp { extern Jit *jit; +extern const float cst_constants[32]; } diff --git a/Core/MIPS/MIPS.cpp b/Core/MIPS/MIPS.cpp index 5362f04b90..02f75117da 100644 --- a/Core/MIPS/MIPS.cpp +++ b/Core/MIPS/MIPS.cpp @@ -15,6 +15,10 @@ // Official git repository and contact information can be found at // https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/. +#include +#include + +#include "math/math_util.h" #include "Common.h" #include "Core/MIPS/MIPS.h" #include "Core/MIPS/MIPSTables.h" @@ -37,6 +41,48 @@ MIPSState *currentMIPS = &mipsr4k; MIPSDebugInterface debugr4k(&mipsr4k); MIPSDebugInterface *currentDebugMIPS = &debugr4k; + +#ifndef M_LOG2E +#define M_E 2.71828182845904523536f +#define M_LOG2E 1.44269504088896340736f +#define M_LOG10E 0.434294481903251827651f +#define M_LN2 0.693147180559945309417f +#define M_LN10 2.30258509299404568402f +#undef M_PI +#define M_PI 3.14159265358979323846f +#define M_PI_2 1.57079632679489661923f +#define M_PI_4 0.785398163397448309616f +#define M_1_PI 0.318309886183790671538f +#define M_2_PI 0.636619772367581343076f +#define M_2_SQRTPI 1.12837916709551257390f +#define M_SQRT2 1.41421356237309504880f +#define M_SQRT1_2 0.707106781186547524401f +#endif + +extern const float cst_constants[32] = { + 0, + std::numeric_limits::max(), // all these are verified on real PSP + sqrtf(2.0f), + sqrtf(0.5f), + 2.0f/sqrtf((float)M_PI), + 2.0f/(float)M_PI, + 1.0f/(float)M_PI, + (float)M_PI/4, + (float)M_PI/2, + (float)M_PI, + (float)M_E, + (float)M_LOG2E, + (float)M_LOG10E, + (float)M_LN2, + (float)M_LN10, + 2*(float)M_PI, + (float)M_PI/6, + log10f(2.0f), + logf(10.0f)/logf(2.0f), + sqrtf(3.0f)/2.0f, +}; + + MIPSState::MIPSState() { MIPSComp::jit = 0; @@ -194,3 +240,4 @@ void MIPSState::Irq() void MIPSState::SWI() { } + diff --git a/Core/MIPS/MIPS.h b/Core/MIPS/MIPS.h index a2777a655c..3c31564946 100644 --- a/Core/MIPS/MIPS.h +++ b/Core/MIPS/MIPS.h @@ -153,3 +153,5 @@ void MIPS_Shutdown(); void MIPS_Irq(); void MIPS_SWI(); + +extern const float cst_constants[32]; diff --git a/Core/MIPS/MIPSIntVFPU.cpp b/Core/MIPS/MIPSIntVFPU.cpp index 8a03d2c694..e106adae5c 100644 --- a/Core/MIPS/MIPSIntVFPU.cpp +++ b/Core/MIPS/MIPSIntVFPU.cpp @@ -1497,35 +1497,11 @@ namespace MIPSInt void Int_Vcst(u32 op) { - static const float constants[32] = - { - 0, - std::numeric_limits::max(), // all these are verified on real PSP - sqrtf(2.0f), - sqrtf(0.5f), - 2.0f/sqrtf((float)M_PI), - 2.0f/(float)M_PI, - 1.0f/(float)M_PI, - (float)M_PI/4, - (float)M_PI/2, - (float)M_PI, - (float)M_E, - (float)M_LOG2E, - (float)M_LOG10E, - (float)M_LN2, - (float)M_LN10, - 2*(float)M_PI, - (float)M_PI/6, - log10f(2.0f), - logf(10.0f)/logf(2.0f), - sqrtf(3.0f)/2.0f, - }; - int conNum = (op >> 16) & 0x1f; int vd = _VD; VectorSize sz = GetVecSize(op); - float c = constants[conNum]; + float c = cst_constants[conNum]; float temp[4] = {c,c,c,c}; ApplyPrefixD(temp, sz); WriteVector(temp, sz, vd); diff --git a/Core/MIPS/x86/CompVFPU.cpp b/Core/MIPS/x86/CompVFPU.cpp index f744e7480a..bb77a2962c 100644 --- a/Core/MIPS/x86/CompVFPU.cpp +++ b/Core/MIPS/x86/CompVFPU.cpp @@ -47,23 +47,6 @@ #define _SIZE ((op>>11 ) & 0x1F) -#ifndef M_LOG2E -#define M_E 2.71828182845904523536f -#define M_LOG2E 1.44269504088896340736f -#define M_LOG10E 0.434294481903251827651f -#define M_LN2 0.693147180559945309417f -#define M_LN10 2.30258509299404568402f -#undef M_PI -#define M_PI 3.14159265358979323846f -#define M_PI_2 1.57079632679489661923f -#define M_PI_4 0.785398163397448309616f -#define M_1_PI 0.318309886183790671538f -#define M_2_PI 0.636619772367581343076f -#define M_2_SQRTPI 1.12837916709551257390f -#define M_SQRT2 1.41421356237309504880f -#define M_SQRT1_2 0.707106781186547524401f -#endif - using namespace Gen; namespace MIPSComp @@ -579,29 +562,6 @@ void Jit::Comp_Vi2f(u32 op) { fpr.ReleaseSpillLocks(); } -static const float cst_constants[32] = { - 0, - std::numeric_limits::max(), // all these are verified on real PSP - sqrtf(2.0f), - sqrtf(0.5f), - 2.0f/sqrtf((float)M_PI), - 2.0f/(float)M_PI, - 1.0f/(float)M_PI, - (float)M_PI/4, - (float)M_PI/2, - (float)M_PI, - (float)M_E, - (float)M_LOG2E, - (float)M_LOG10E, - (float)M_LN2, - (float)M_LN10, - 2*(float)M_PI, - (float)M_PI/6, - log10f(2.0f), - logf(10.0f)/logf(2.0f), - sqrtf(3.0f)/2.0f, -}; - void Jit::Comp_Vcst(u32 op) { CONDITIONAL_DISABLE;