diff --git a/Common/ArmEmitter.cpp b/Common/ArmEmitter.cpp
index 8f7a1e843e..35db2b0f5a 100644
--- a/Common/ArmEmitter.cpp
+++ b/Common/ArmEmitter.cpp
@@ -596,20 +596,20 @@ void ARMXEmitter::MRS (ARMReg dest)
 	Write32(condition | (16 << 20) | (15 << 16) | (dest << 12));
 }
 
-void ARMXEmitter::WriteStoreOp(u32 op, ARMReg result, ARMReg base, Operand2 op2)
+void ARMXEmitter::WriteStoreOp(u32 op, ARMReg src, ARMReg dest, Operand2 op2)
 {
 	if (op2.GetData() == 0) // set the preindex bit, but not the W bit!
-		Write32(condition | 0x01800000 | (op << 20) | (base << 16) | (result << 12) | op2.Imm12());
+		Write32(condition | 0x01800000 | (op << 20) | (src << 16) | (dest << 12) | op2.Imm12());
 	else
-		Write32(condition | (op << 20) | (3 << 23) | (base << 16) | (result << 12) | op2.Imm12()); 
+		Write32(condition | (op << 20) | (3 << 23) | (src << 16) | (dest << 12) | op2.Imm12()); 
 }
-void ARMXEmitter::STR  (ARMReg result, ARMReg base, Operand2 op) { WriteStoreOp(0x40, result, base, op);}
+void ARMXEmitter::STR  (ARMReg result, ARMReg base, Operand2 op) { WriteStoreOp(0x40, base, result, op);}
 void ARMXEmitter::STRH (ARMReg result, ARMReg base, Operand2 op)
 {
 	u8 Imm = op.Imm8();
 	Write32(condition | (0x04 << 20) | (base << 16) | (result << 12) | ((Imm >> 4) << 8) | (0xB << 4) | (Imm & 0x0F));
 }
-void ARMXEmitter::STRB (ARMReg result, ARMReg base, Operand2 op) { WriteStoreOp(0x44, result, base, op);}
+void ARMXEmitter::STRB (ARMReg result, ARMReg base, Operand2 op) { WriteStoreOp(0x44, base, result, op);}
 void ARMXEmitter::STR  (ARMReg result, ARMReg base, Operand2 op2, bool Index, bool Add)
 {
 	Write32(condition | (0x60 << 20) | (Index << 24) | (Add << 23) | (base << 16) | (result << 12) | op2.IMMSR());
diff --git a/Common/ArmEmitter.h b/Common/ArmEmitter.h
index cc66393422..c287bd6aef 100644
--- a/Common/ArmEmitter.h
+++ b/Common/ArmEmitter.h
@@ -178,7 +178,7 @@ public:
 		Value = base;
 	}
 
-	Operand2(u8 shift, ShiftType type, ARMReg base)// For IMM shifted register
+	Operand2(ARMReg base, ShiftType type, u8 shift)// For IMM shifted register
 	{
 		if(shift == 32) shift = 0;
 		switch (type)
@@ -352,7 +352,7 @@ private:
 	u32 condition;
 	std::vector<LiteralPool> currentLitPool;
 
-	void WriteStoreOp(u32 op, ARMReg dest, ARMReg src, Operand2 op2);
+	void WriteStoreOp(u32 op, ARMReg src, ARMReg dest, Operand2 op2);
 	void WriteRegStoreOp(u32 op, ARMReg dest, bool WriteBack, u16 RegList);
 	void WriteShiftedDataOp(u32 op, bool SetFlags, ARMReg dest, ARMReg src, ARMReg op2);
 	void WriteShiftedDataOp(u32 op, bool SetFlags, ARMReg dest, ARMReg src, Operand2 op2);
diff --git a/Core/MIPS/ARM/ArmAsm.cpp b/Core/MIPS/ARM/ArmAsm.cpp
index 2ec66f05be..9ea153b522 100644
--- a/Core/MIPS/ARM/ArmAsm.cpp
+++ b/Core/MIPS/ARM/ArmAsm.cpp
@@ -165,7 +165,7 @@ void Jit::GenerateFixedCode()
 				// IDEA - we have 26 bits, why not just use offsets from base of code?
 				// Another idea: Shift the bloc number left by two in the op, this would let us do
 				// LDR(R0, R9, R0, true, true); here, replacing the next instructions.
-				ADD(R0, R9, Operand2(2, ST_LSL, R0));
+				ADD(R0, R9, Operand2(R0, ST_LSL, 2));
 				LDR(R0, R0);
 				B(R0);
 			SetCC(CC_AL);
diff --git a/Core/MIPS/ARM/ArmCompALU.cpp b/Core/MIPS/ARM/ArmCompALU.cpp
index b0020a1a9a..fa4618d9cf 100644
--- a/Core/MIPS/ARM/ArmCompALU.cpp
+++ b/Core/MIPS/ARM/ArmCompALU.cpp
@@ -287,7 +287,7 @@ namespace MIPSComp
 		int sa = _SA;
 		
 		gpr.MapDirtyIn(rd, rt);
-		MOV(gpr.R(rd), Operand2(sa, shiftType, gpr.R(rt)));
+		MOV(gpr.R(rd), Operand2(gpr.R(rt), shiftType, sa));
 	}
 
 	void Jit::CompShiftVar(u32 op, ArmGen::ShiftType shiftType)
@@ -299,7 +299,7 @@ namespace MIPSComp
 		{
 			gpr.MapDirtyIn(rd, rt);
 			int sa = gpr.GetImm(rs) & 0x1F;
-			MOV(gpr.R(rd), Operand2(sa, shiftType, gpr.R(rt)));
+			MOV(gpr.R(rd), Operand2(gpr.R(rt), shiftType, sa));
 			return;
 		}
 		gpr.MapDirtyInIn(rd, rs, rt);
@@ -362,7 +362,7 @@ namespace MIPSComp
 			if (useUBFXandBFI) {
 				UBFX(gpr.R(rt), gpr.R(rs), pos, size);
 			} else {
-				MOV(gpr.R(rt), Operand2(pos, ST_LSR, gpr.R(rs)));
+				MOV(gpr.R(rt), Operand2(gpr.R(rs), ST_LSR, pos));
 				ANDI2R(gpr.R(rt), gpr.R(rt), mask, R0);
 			}
 			break;
@@ -393,7 +393,7 @@ namespace MIPSComp
 					} else {
 						gpr.MapDirtyIn(rt, rs, false);
 						ANDI2R(R0, gpr.R(rs), sourcemask, R1);
-						MOV(R0, Operand2(pos, ST_LSL, R0));
+						MOV(R0, Operand2(R0, ST_LSL, pos));
 						ANDI2R(gpr.R(rt), gpr.R(rt), destmask, R1);
 						ORR(gpr.R(rt), gpr.R(rt), R0);
 					}
diff --git a/Core/MIPS/ARM/ArmCompLoadStore.cpp b/Core/MIPS/ARM/ArmCompLoadStore.cpp
index 5ec605200e..cfe3fda2fd 100644
--- a/Core/MIPS/ARM/ArmCompLoadStore.cpp
+++ b/Core/MIPS/ARM/ArmCompLoadStore.cpp
@@ -150,10 +150,16 @@ namespace MIPSComp
 					// We can compute the full address at compile time. Kickass.
 					u32 addr = (offset + gpr.GetImm(rs)) & 0x3FFFFFFF;
 					// Must be OK even if rs == rt since we have the value from imm already.
-					gpr.MapReg(rt, load ? MAP_NOINIT | MAP_DIRTY : 0);
+					if (shifter && !load)
+						gpr.MapReg(rt, MAP_DIRTY);
+					else
+						gpr.MapReg(rt, load ? ( MAP_NOINIT | MAP_DIRTY) : 0);
 					MOVI2R(R0, addr);
 				} else {
-					load ? gpr.MapDirtyIn(rt, rs) : gpr.MapInIn(rt, rs);
+					if (shifter && !load)
+						gpr.MapDirtyIn(rt, rs, false);
+					else
+						load ? gpr.MapDirtyIn(rt, rs) : gpr.MapInIn(rt, rs);
 					SetR0ToEffectiveAddress(rs, offset);
 				}
 				switch (o)
@@ -162,12 +168,12 @@ namespace MIPSComp
 				case 34:
 					AND(gpr.R(rt), gpr.R(rt), 0x00ffffff >> shift);
 					LDR(R0, R11, R0, true, true);
-					ORR(gpr.R(rt), gpr.R(rt), Operand2(24 - shift, ST_LSL, R0));
+					ORR(gpr.R(rt), gpr.R(rt), Operand2(R0, ST_LSL, 24 - shift));
 					break;
 				case 38:
 					AND(gpr.R(rt), gpr.R(rt), 0xffffff00 << (24 - shift));
 					LDR(R0, R11, R0, true, true);
-					ORR(gpr.R(rt), gpr.R(rt), Operand2(shift, ST_LSR, R0));
+					ORR(gpr.R(rt), gpr.R(rt), Operand2(R0, ST_LSR, shift));
 					break;
 				case 35: LDR  (gpr.R(rt), R11, R0, true, true); break;
 				case 37: LDRH (gpr.R(rt), R11, R0, true, true); break;
@@ -176,16 +182,16 @@ namespace MIPSComp
 				case 32: LDRSB(gpr.R(rt), R11, R0, true, true); break;
 				// Store
 				case 42:
-					LSR(gpr.R(rt), gpr.R(rt), 24-shift);
-					AND(R0, R0, 0xffffff00 << shift);
-					ORR(R0, R0, gpr.R(rt));
-					STR(gpr.R(rt), R11, R0, true, true);
+					LDR(R1, R11, R0, true, true);
+					AND(R1, R1, 0xffffff00 << shift);
+					ORR(R1, R1, Operand2(gpr.R(rt), ST_LSR, 24 - shift));
+					STR(R1, R11, R0, true, true);
 					break;
 				case 46:
-					LSL(gpr.R(rt), gpr.R(rt), shift);
-					AND(R0, R0, 0x00ffffff >> (24 - shift));
-					ORR(R0, R0, gpr.R(rt));
-					STR(gpr.R(rt), R11, R0, true, true);
+					LDR(R1, R11, R0, true, true);
+					AND(R1, R1, 0x00ffffff >> (24 - shift));
+					ORR(R1, R1, Operand2(gpr.R(rt), ST_LSL, shift));
+					STR(R1, R11, R0, true, true);
 					break;
 				case 43: STR  (gpr.R(rt), R11, R0, true, true); break;
 				case 41: STRH (gpr.R(rt), R11, R0, true, true); break;
diff --git a/Core/MIPS/ARM/ArmRegCacheFPU.cpp b/Core/MIPS/ARM/ArmRegCacheFPU.cpp
index 0bc0764018..98a0f5bca8 100644
--- a/Core/MIPS/ARM/ArmRegCacheFPU.cpp
+++ b/Core/MIPS/ARM/ArmRegCacheFPU.cpp
@@ -192,7 +192,7 @@ void ArmRegCacheFPU::FlushArmReg(ARMReg r) {
 		if (ar[reg].isDirty && mr[ar[reg].mipsReg].loc == ML_ARMREG)
 		{
 			//INFO_LOG(HLE, "Flushing ARM reg %i", reg);
-			emit->VSTR(CTXREG, r, GetMipsRegOffset(ar[reg].mipsReg));
+			emit->VSTR(r, CTXREG, GetMipsRegOffset(ar[reg].mipsReg));
 		}
 		// IMMs won't be in an ARM reg.
 		mr[ar[reg].mipsReg].loc = ML_MEM;
@@ -218,7 +218,7 @@ void ArmRegCacheFPU::FlushR(MIPSReg r) {
 		}
 		if (ar[mr[r].reg].isDirty) {
 			//INFO_LOG(HLE, "Flushing dirty reg %i", mr[r].reg);
-			emit->VSTR(CTXREG, (ARMReg)(mr[r].reg + S0), GetMipsRegOffset(r));
+			emit->VSTR((ARMReg)(mr[r].reg + S0), CTXREG, GetMipsRegOffset(r));
 			ar[mr[r].reg].isDirty = false;
 		}
 		ar[mr[r].reg].mipsReg = -1;