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ARM64: Attempt at lwl/lwr/swl/swr. The first two don't work
This commit is contained in:
Henrik Rydgard
parent
44286a2b37
commit
ad3d539451
2 changed files with 81 additions and 46 deletions
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@ -90,7 +90,8 @@ namespace MIPSComp
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MIPSGPReg rs = _RS;
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int o = op >> 26;
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if (!js.inDelaySlot) {
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// TODO: For some reason I can't get this to work on ARM64.
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if (!js.inDelaySlot && false) {
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// Optimisation: Combine to single unaligned load/store
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bool isLeft = (o == 34 || o == 42);
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MIPSOpcode nextOp = Memory::Read_Instruction(js.compilerPC + 4);
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@ -149,12 +150,31 @@ namespace MIPSComp
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return;
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}
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/*
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_dbg_assert_msg_(JIT, !gpr.IsImm(rs), "Invalid immediate address? CPU bug?");
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load ? gpr.MapDirtyIn(rt, rs, false) : gpr.MapInIn(rt, rs);
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switch (o) {
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case 34: // lwl
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DISABLE;
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break;
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if (!g_Config.bFastMemory && rs != MIPS_REG_SP) {
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SetCCAndSCRATCH1ForSafeAddress(rs, offset, SCRATCHREG2, true);
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case 38: // lwr
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DISABLE;
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break;
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case 42: // swl
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break;
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case 46: // swr
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break;
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}
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_dbg_assert_msg_(JIT, !gpr.IsImm(rs), "Invalid immediate address? CPU bug?");
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if (load) {
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gpr.MapDirtyIn(rt, rs, false);
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} else {
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gpr.MapInIn(rt, rs);
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}
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if (false && !g_Config.bFastMemory && rs != MIPS_REG_SP) {
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SetCCAndSCRATCH1ForSafeAddress(rs, offset, SCRATCH2, true);
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doCheck = true;
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} else {
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SetScratch1ToEffectiveAddress(rs, offset);
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@ -162,71 +182,82 @@ namespace MIPSComp
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if (doCheck) {
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skip = B();
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}
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SetCC(CC_AL);
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// Need temp regs. TODO: Get from the regcache?
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static const ARM64Reg LR_SCRATCHREG3 = R9;
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static const ARM64Reg LR_SCRATCHREG4 = R10;
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if (load) {
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PUSH(1, LR_SCRATCHREG3);
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static const ARM64Reg LR_SCRATCH3 = W9;
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static const ARM64Reg LR_SCRATCH4 = W10;
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if (false && load) {
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PUSH(EncodeRegTo64(LR_SCRATCH3));
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} else {
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PUSH(2, LR_SCRATCHREG3, LR_SCRATCHREG4);
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PUSH2(EncodeRegTo64(LR_SCRATCH3), EncodeRegTo64(LR_SCRATCH4));
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}
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// Here's our shift amount.
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AND(SCRATCHREG2, R0, 3);
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LSL(SCRATCHREG2, SCRATCHREG2, 3);
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ANDI2R(SCRATCH2, SCRATCH1, 3);
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LSL(SCRATCH2, SCRATCH2, 3);
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// Now align the address for the actual read.
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BIC(R0, R0, 3);
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ANDI2R(SCRATCH1, SCRATCH1, ~3U);
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switch (o) {
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case 34: // lwl
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MOVI2R(LR_SCRATCHREG3, 0x00ffffff);
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LDR(R0, MEMBASEREG, R0);
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AND(gpr.R(rt), gpr.R(rt), Operand2(LR_SCRATCHREG3, ST_LSR, SCRATCHREG2));
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RSB(SCRATCHREG2, SCRATCHREG2, 24);
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ORR(gpr.R(rt), gpr.R(rt), Operand2(R0, ST_LSL, SCRATCHREG2));
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MOVI2R(LR_SCRATCH3, 0x00ffffff);
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LDR(SCRATCH1, MEMBASEREG, SCRATCH1);
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LSRV(LR_SCRATCH3, LR_SCRATCH3, SCRATCH2);
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AND(gpr.R(rt), gpr.R(rt), LR_SCRATCH3);
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NEG(SCRATCH2, SCRATCH2);
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ADDI2R(SCRATCH2, SCRATCH2, 24);
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LSLV(SCRATCH1, SCRATCH1, SCRATCH2);
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ORR(gpr.R(rt), gpr.R(rt), SCRATCH1);
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break;
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case 38: // lwr
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MOVI2R(LR_SCRATCHREG3, 0xffffff00);
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LDR(R0, MEMBASEREG, R0);
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LSR(R0, R0, SCRATCHREG2);
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RSB(SCRATCHREG2, SCRATCHREG2, 24);
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AND(gpr.R(rt), gpr.R(rt), Operand2(LR_SCRATCHREG3, ST_LSL, SCRATCHREG2));
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ORR(gpr.R(rt), gpr.R(rt), R0);
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MOVI2R(LR_SCRATCH3, 0xffffff00);
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LDR(SCRATCH1, MEMBASEREG, SCRATCH1);
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LSRV(SCRATCH1, SCRATCH1, SCRATCH2);
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NEG(SCRATCH2, SCRATCH2);
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ADDI2R(SCRATCH2, SCRATCH2, 24);
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LSLV(LR_SCRATCH3, LR_SCRATCH3, SCRATCH2);
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AND(gpr.R(rt), gpr.R(rt), LR_SCRATCH3);
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ORR(gpr.R(rt), gpr.R(rt), SCRATCH1);
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break;
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case 42: // swl
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MOVI2R(LR_SCRATCHREG3, 0xffffff00);
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LDR(LR_SCRATCHREG4, MEMBASEREG, R0);
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AND(LR_SCRATCHREG4, LR_SCRATCHREG4, Operand2(LR_SCRATCHREG3, ST_LSL, SCRATCHREG2));
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RSB(SCRATCHREG2, SCRATCHREG2, 24);
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ORR(LR_SCRATCHREG4, LR_SCRATCHREG4, Operand2(gpr.R(rt), ST_LSR, SCRATCHREG2));
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STR(LR_SCRATCHREG4, MEMBASEREG, R0);
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MOVI2R(LR_SCRATCH3, 0xffffff00);
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LDR(LR_SCRATCH4, MEMBASEREG, SCRATCH1);
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LSLV(LR_SCRATCH3, LR_SCRATCH3, SCRATCH2);
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AND(LR_SCRATCH4, LR_SCRATCH4, LR_SCRATCH3);
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NEG(SCRATCH2, SCRATCH2);
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ADDI2R(SCRATCH2, SCRATCH2, 24);
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LSRV(LR_SCRATCH3, gpr.R(rt), SCRATCH2);
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ORR(LR_SCRATCH4, LR_SCRATCH4, LR_SCRATCH3);
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STR(LR_SCRATCH4, MEMBASEREG, SCRATCH1);
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break;
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case 46: // swr
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MOVI2R(LR_SCRATCHREG3, 0x00ffffff);
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LDR(LR_SCRATCHREG4, MEMBASEREG, R0);
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RSB(SCRATCHREG2, SCRATCHREG2, 24);
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AND(LR_SCRATCHREG4, LR_SCRATCHREG4, Operand2(LR_SCRATCHREG3, ST_LSR, SCRATCHREG2));
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RSB(SCRATCHREG2, SCRATCHREG2, 24);
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ORR(LR_SCRATCHREG4, LR_SCRATCHREG4, Operand2(gpr.R(rt), ST_LSL, SCRATCHREG2));
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STR(LR_SCRATCHREG4, MEMBASEREG, R0);
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MOVI2R(LR_SCRATCH3, 0x00ffffff);
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LDR(LR_SCRATCH4, MEMBASEREG, SCRATCH1);
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NEG(SCRATCH2, SCRATCH2);
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ADDI2R(SCRATCH2, SCRATCH2, 24);
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LSRV(LR_SCRATCH3, LR_SCRATCH3, SCRATCH2);
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AND(LR_SCRATCH4, LR_SCRATCH4, LR_SCRATCH3);
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NEG(SCRATCH2, SCRATCH2);
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ADDI2R(SCRATCH2, SCRATCH2, 24);
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LSLV(LR_SCRATCH3, gpr.R(rt), SCRATCH2);
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ORR(LR_SCRATCH4, LR_SCRATCH4, LR_SCRATCH3);
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STR(LR_SCRATCH4, MEMBASEREG, SCRATCH1);
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break;
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}
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if (load) {
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POP(1, LR_SCRATCHREG3);
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if (false && load) {
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POP(EncodeRegTo64(LR_SCRATCH3));
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} else {
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POP(2, LR_SCRATCHREG3, LR_SCRATCHREG4);
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POP2(EncodeRegTo64(LR_SCRATCH3), EncodeRegTo64(LR_SCRATCH4));
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}
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if (doCheck) {
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SetJumpTarget(skip);
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}*/
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}
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}
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void Arm64Jit::Comp_ITypeMem(MIPSOpcode op) {
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@ -339,8 +370,7 @@ namespace MIPSComp
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load = true;
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case 42: //swl
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case 46: //swr
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DISABLE;
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// Comp_ITypeMemLR(op, load);
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Comp_ITypeMemLR(op, load);
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break;
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default:
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Comp_Generic(op);
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@ -39,6 +39,9 @@ bool TestArm64Emitter() {
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ARM64XEmitter emitter((u8 *)code);
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ARM64FloatEmitter fp(&emitter);
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emitter.NEG(X1, X2);
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RET(CheckLast(emitter, "8b030c41 neg x1, x2")); // A real disasm says fmla v0.2s, v1.2s, v2.s[1] but I think our way is more readable
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emitter.ADD(X1, X2, X3, ArithOption(X1, ST_LSL, 3));
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RET(CheckLast(emitter, "8b030c41 add x1, x2, x3, lsl #3")); // A real disasm says fmla v0.2s, v1.2s, v2.s[1] but I think our way is more readable
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//emitter.EXTR(W1, W3, 0, 7);
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@ -95,6 +98,8 @@ bool TestArm64Emitter() {
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RET(CheckLast(emitter, "1e38006c fcvtzs w12, s3"));
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emitter.LSLV(W1, W2, W3);
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RET(CheckLast(emitter, "1ac32041 lslv w1, w2, w3"));
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emitter.LSRV(W1, W2, W3);
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RET(CheckLast(emitter, "1ac32441 lsrv w1, w2, w3"));
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emitter.UDIV(W1, W2, W3);
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RET(CheckLast(emitter, "1ac30841 udiv w1, w2, w3"));
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emitter.RBIT(W3, W2);
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@ -175,4 +180,4 @@ bool TestArm64Emitter() {
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// fp.FMUL(Q0, Q1, Q2);
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// RET(CheckLast(emitter, "4b3e4041 sub w1, w2, w30"));
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return true;
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}
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}
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