mirror of
https://github.com/hrydgard/ppsspp.git
synced 2025-04-02 11:01:50 -04:00
Major ARM disassembler improvements, will make debugging the JIT easier
This commit is contained in:
Henrik Rydgard
parent
174b5187e6
commit
ab9cd99d0f
3 changed files with 243 additions and 31 deletions
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@ -1613,7 +1613,7 @@ void ARMXEmitter::VADD(u32 Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
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bool register_quad = Vd >= Q0;
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if (Size & F_32)
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Write32((0xF2 << 24) | EncodeVn(Vn) | EncodeVd(Vd) | (0xD0 << 4) | (register_quad << 6) | EncodeVm(Vm));
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Write32((0xF2 << 24) | EncodeVn(Vn) | EncodeVd(Vd) | (0xD << 8) | (register_quad << 6) | EncodeVm(Vm));
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else
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Write32((0xF2 << 24) | (encodedSize(Size) << 20) | EncodeVn(Vn) | EncodeVd(Vd) \
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| (0x8 << 8) | (register_quad << 6) | EncodeVm(Vm));
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202
ext/disarm.cpp
202
ext/disarm.cpp
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@ -92,26 +92,39 @@ static const char *CCFlagsStr[] = {
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};
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int GetVd(uint32_t op, bool quad = false, bool dbl = false) {
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int val;
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if (!quad && !dbl) {
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return ((op >> 22) & 1) | ((op >> 11) & 0x1E);
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val = ((op >> 22) & 1) | ((op >> 11) & 0x1E);
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} else {
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val = ((op >> 18) & 0x10) | ((op >> 12) & 0xF);
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}
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return 0;
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if (quad)
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val >>= 1;
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return val;
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}
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int GetVn(uint32_t op, bool quad = false, bool dbl = false) {
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int val;
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if (!quad && !dbl) {
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return ((op >> 7) & 1) | ((op >> 15) & 0x1E);
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} else if (dbl) {
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return ((op >> 16) & 0xF) | ((op >> 3) & 0x10);
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val = ((op >> 7) & 1) | ((op >> 15) & 0x1E);
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} else {
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val = ((op >> 16) & 0xF) | ((op >> 3) & 0x10);
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}
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return 0;
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if (quad)
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val >>= 1;
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return val;
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}
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int GetVm(uint32_t op, bool quad = false, bool dbl = false) {
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int val;
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if (!quad && !dbl) {
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return ((op >> 5) & 1) | ((op << 1) & 0x1E);
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val = ((op >> 5) & 1) | ((op << 1) & 0x1E);
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} else {
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val = ((op >> 1) & 0x10) | (op & 0xF);
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}
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return 0;
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if (quad)
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val >>= 1;
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return val;
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}
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@ -214,12 +227,16 @@ bool DisasmVFP(uint32_t op, char *text) {
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int part2 = ((op >> 9) & 0x7) ;
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int part3 = ((op >> 20) & 0x3) ;
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if (part3 == 3 && part2 == 5 && part1 == 0x1D && (op & (1<<6))) {
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// VMOV
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// VMOV, VCMP
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int vn = GetVn(op);
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if (vn != 1 && vn != 3) {
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int vm = GetVm(op);
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int vd = GetVd(op);
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sprintf(text, "VMOV%s s%i, s%i", cond, vd, vm);
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const char *name = "VMOV";
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if (op & 0x40000)
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name = (op & 0x80) ? "VCMPE" : "VCMP";
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sprintf(text, "%s%s s%i, s%i", name, cond, vd, vm);
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return true;
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}
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}
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@ -232,13 +249,18 @@ bool DisasmVFP(uint32_t op, char *text) {
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int opc1 = (op >> 20) & 0xFB;
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int opc2 = (op >> 4) & 0xAC;
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for (int i = 0; i < 16; i++) {
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if (ArmGen::VFPOps[i][0].opc1 == opc1 && ArmGen::VFPOps[i][0].opc2 == opc2) {
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// What the hell?
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int fixed_opc2 = opc2;
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if (!(ArmGen::VFPOps[i][0].opc2 & 0x8))
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fixed_opc2 &= 0xA7;
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if (ArmGen::VFPOps[i][0].opc1 == opc1 && ArmGen::VFPOps[i][0].opc2 == fixed_opc2) {
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opnum = i;
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break;
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}
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}
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if (opnum < 0)
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return false;
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char c = double_reg ? 'd' : 's';
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switch (opnum) {
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case 8:
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case 10:
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@ -251,8 +273,9 @@ bool DisasmVFP(uint32_t op, char *text) {
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int vd = GetVd(op, quad_reg, double_reg);
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int vn = GetVn(op, quad_reg, true);
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int vm = GetVm(op, quad_reg, double_reg);
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if (opnum == 8 && vn == 0x11) opnum += 3;
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sprintf(text, "%s%s s%i, s%i", ArmGen::VFPOpNames[opnum], cond, vd, vm);
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if (opnum == 8 && vn == 0x11)
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opnum += 3;
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sprintf(text, "%s%s %c%i, %c%i", ArmGen::VFPOpNames[opnum], cond, c, vd, c, vm);
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return true;
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}
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default:
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@ -261,7 +284,7 @@ bool DisasmVFP(uint32_t op, char *text) {
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int vd = GetVd(op, quad_reg, double_reg);
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int vn = GetVn(op, quad_reg, double_reg);
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int vm = GetVm(op, quad_reg, double_reg);
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sprintf(text, "%s%s s%i, s%i, s%i", ArmGen::VFPOpNames[opnum], cond, vd, vn, vm);
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sprintf(text, "%s%s %c%i, %c%i, %c%i", ArmGen::VFPOpNames[opnum], cond, c, vd, c, vn, c, vm);
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return true;
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}
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}
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@ -272,13 +295,122 @@ bool DisasmVFP(uint32_t op, char *text) {
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#endif
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return false;
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}
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static const char *GetSizeString(int sz) {
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switch (sz) {
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case 0:
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return "8";
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case 1:
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return "16";
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case 2:
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return "32";
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case 3:
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return "64";
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default:
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return "(err)";
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}
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}
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static const char *GetISizeString(int sz) {
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switch (sz) {
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case 0:
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return "i8";
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case 1:
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return "i16";
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case 2:
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return "i32";
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case 3:
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return "i64";
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default:
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return "(err)";
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}
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}
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static int GetRegCount(int type) {
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switch (type) {
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case 7: return 1;
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case 10: return 2;
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case 6: return 3;
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case 4: return 4;
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default:
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return 0;
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}
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}
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// VLD1 / VST1
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static bool DisasmNeonLDST(uint32_t op, char *text) {
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bool load = (op >> 21) & 1;
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int Rn = (op >> 16) & 0xF;
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int Rm = (op & 0xF);
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int Vd = GetVd(op, false, true);
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int sz = (op >> 6) & 3;
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int regCount = GetRegCount((op >> 8) & 0xF);
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int startReg = Vd;
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int endReg = Vd + regCount - 1;
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if (startReg == endReg)
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sprintf(text, "V%s1.%s {d%i}, [r%i]", load ? "LD" : "ST", GetSizeString(sz), startReg, Rn);
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else
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sprintf(text, "V%s1.%s {d%i-d%i}, [r%i]", load ? "LD" : "ST", GetSizeString(sz), startReg, endReg, Rn);
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return true;
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}
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static bool DisasmNeonF3(uint32_t op, char *text) {
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sprintf(text, "NEON F3");
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return true;
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}
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static bool DisasmNeonF2F3(uint32_t op, char *text) {
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sprintf(text, "NEON F2");
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if (((op >> 20) & 0xFFC) == 0xF20 || ((op >> 20) & 0xFFC) == 0xF30) {
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bool quad = ((op >> 6) & 1);
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int size = (op >> 20) & 3;
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int type = (op >> 8) & 0xF;
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char r = quad ? 'q' : 'd';
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const char *opname = "(unk)";
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switch ((op >> 20) & 0xFF) {
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case 0x20:
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if (op & 0x10)
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opname = "MLA";
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else
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opname = "ADD";
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break;
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case 0x22:
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if (op & 0x10)
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opname = "MLS";
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else
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opname = "ADD";
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break;
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case 0x31:
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if (op & 0x100)
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opname = "MLS";
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else
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opname = "SUB";
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break;
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case 0x30:
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opname = "MUL";
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break;
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}
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const char *szname = GetISizeString(size);
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if (type == 0xD)
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szname = "f32";
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sprintf(text, "V%s.%s %c%i, %c%i, %c%i", opname, szname, r, GetVd(op, quad, true), r, GetVn(op, quad, true), r, GetVm(op, quad, true));
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}
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return true;
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}
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static bool DisasmNeon(uint32_t op, char *text) {
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switch (op >> 24) {
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case 0xF4:
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return DisasmNeonLDST(op, text);
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case 0xF2:
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case 0xF3:
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return DisasmNeonF2F3(op, text);
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}
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return false;
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}
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@ -595,7 +727,15 @@ instr_disassemble(word instr, address addr, pDisOptions opts) {
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break;
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}
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case 3:
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/* SWP or MRS/MSR or data processing */
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if (instr >> 24 == 0xF3) {
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if (!DisasmNeon(instr, result.text)) {
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goto lUndefined;
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break;
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}
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result.undefined = 0;
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return &result;
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}
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/* SWP or MRS/MSR or data processing */
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// hrydgard addition: MOVW/MOVT
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if ((instr & 0x0FF00000) == 0x03000000) {
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mnemonic = "MOVW";
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@ -657,7 +797,15 @@ lMaybeLDRHetc:
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}
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#endif
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case 2:
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/* data processing */
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if (instr >> 24 == 0xF2) {
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if (!DisasmNeon(instr, result.text)) {
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goto lUndefined;
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break;
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}
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result.undefined = 0;
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return &result;
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}
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/* data processing */
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{ word op21 = instr&(15<<21);
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if ((op21==(2<<21) || (op21==(4<<21))) /* ADD or SUB */
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&& ((instr&(RNbits+Ibit+Sbit))==RN(15)+Ibit) /* imm, no S */
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@ -692,7 +840,15 @@ lMaybeLDRHetc:
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}
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break;
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case 4:
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case 5:
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if (instr >> 24 == 0xF4) {
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if (!DisasmNeon(instr, result.text)) {
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goto lUndefined;
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break;
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}
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result.undefined = 0;
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return &result;
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}
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case 5:
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case 6:
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case 7:
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/* undefined or STR/LDR */
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@ -733,12 +889,10 @@ lMaybeLDRHetc:
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case 13:
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case 14: // FPU
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{
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char text[128];
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if (!DisasmVFP(instr, text)) {
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if (!DisasmVFP(instr, result.text)) {
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goto lUndefined;
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break;
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}
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strcpy(result.text, text);
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result.undefined = 0;
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return &result;
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}
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@ -31,6 +31,7 @@
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#include <string>
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#include "base/NativeApp.h"
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#include "Common/CPUDetect.h"
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#include "Common/ArmEmitter.h"
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#include "ext/disarm.h"
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#include "math/math_util.h"
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@ -260,14 +261,30 @@ bool TestArmEmitter() {
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RET(CheckLast(emitter, "ed4c2a09 VSTR s5, [r12, #-36]"));
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emitter.VADD(S1, S2, S3);
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RET(CheckLast(emitter, "ee710a21 VADD s1, s2, s3"));
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emitter.VADD(D1, D2, D3);
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RET(CheckLast(emitter, "ee321b03 VADD d1, d2, d3"));
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emitter.VSUB(S1, S2, S3);
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RET(CheckLast(emitter, "ee710a61 VSUB s1, s2, s3"));
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emitter.VMUL(S7, S8, S9);
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RET(CheckLast(emitter, "ee643a24 VMUL s7, s8, s9"));
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emitter.VMUL(S0, S5, S10);
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RET(CheckLast(emitter, "ee220a85 VMUL s0, s5, s10"));
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emitter.VNMUL(S7, S8, S9);
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RET(CheckLast(emitter, "ee643a64 VNMUL s7, s8, s9"));
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emitter.VMLA(S7, S8, S9);
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RET(CheckLast(emitter, "ee443a24 VMLA s7, s8, s9"));
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emitter.VNMLA(S7, S8, S9);
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RET(CheckLast(emitter, "ee543a64 VNMLA s7, s8, s9"));
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emitter.VNMLS(S7, S8, S9);
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RET(CheckLast(emitter, "ee543a24 VNMLS s7, s8, s9"));
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emitter.VABS(S1, S2);
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RET(CheckLast(emitter, "eef00ac1 VABS s1, s2"));
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emitter.VMOV(S1, S2);
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RET(CheckLast(emitter, "eef00a41 VMOV s1, s2"));
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emitter.VCMP(S1, S2);
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RET(CheckLast(emitter, "eef40a41 VCMP s1, s2"));
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emitter.VCMPE(S1, S2);
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RET(CheckLast(emitter, "eef40ac1 VCMPE s1, s2"));
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emitter.VSQRT(S1, S2);
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RET(CheckLast(emitter, "eef10ac1 VSQRT s1, s2"));
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emitter.VDIV(S1, S2, S3);
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@ -289,6 +306,44 @@ bool TestArmEmitter() {
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emitter.VMOV(S3, S6);
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RET(CheckLast(emitter, "eef01a43 VMOV s3, s6"));
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/*
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// These are only implemented in the neon-vfpu branch. will cherrypick later.
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emitter.VMOV_imm(I_32, R0, VIMM___x___x, 0xF3);
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emitter.VMOV_imm(I_8, R0, VIMMxxxxxxxx, 0xF3);
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emitter.VMOV_immf(Q0, 1.0f);
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RET(CheckLast(emitter, "eebd0a60 VMOV Q0, 1.0"));
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emitter.VMOV_immf(Q0, -1.0f);
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emitter.VBIC_imm(I_32, R0, VIMM___x___x, 0xF3);
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emitter.VMVN_imm(I_32, R0, VIMM___x___x, 0xF3);
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emitter.VPADD(F_32, D0, D0, D0);
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emitter.VMOV(Q14, Q2);
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*/
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emitter.VMOV(S3, S6);
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RET(CheckLast(emitter, "eef01a43 VMOV s3, s6"));
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emitter.VLD1(I_32, D19, R3, 2, ALIGN_NONE, R_PC);
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RET(CheckLast(emitter, "f4633a8f VLD1.32 {d19-d20}, [r3]"));
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emitter.VST1(I_32, D23, R9, 1, ALIGN_NONE, R_PC);
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RET(CheckLast(emitter, "f449778f VST1.32 {d23}, [r9]"));
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emitter.VADD(I_8, D3, D4, D19);
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RET(CheckLast(emitter, "f2043823 VADD.i8 d3, d4, d19"));
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emitter.VADD(I_32, D3, D4, D19);
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RET(CheckLast(emitter, "f2243823 VADD.i32 d3, d4, d19"));
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emitter.VADD(F_32, D3, D4, D19);
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RET(CheckLast(emitter, "f2043d23 VADD.f32 d3, d4, d19"));
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emitter.VSUB(I_16, Q5, Q6, Q15);
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RET(CheckLast(emitter, "f31ca86e VSUB.i16 q5, q6, q15"));
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emitter.VMUL(F_32, Q1, Q2, Q3);
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RET(CheckLast(emitter, "f3042d56 VMUL.f32 q1, q2, q3"));
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emitter.VADD(F_32, Q1, Q2, Q3);
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RET(CheckLast(emitter, "f2042d46 VADD.f32 q1, q2, q3"));
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emitter.VMLA(F_32, Q1, Q2, Q3);
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RET(CheckLast(emitter, "f2042d56 VMLA.f32 q1, q2, q3"));
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emitter.VMLS(F_32, Q1, Q2, Q3);
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RET(CheckLast(emitter, "f2242d56 VMLS.f32 q1, q2, q3"));
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emitter.VMLS(I_16, Q1, Q2, Q3);
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RET(CheckLast(emitter, "f3142946 VMLS.i16 q1, q2, q3"));
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return true;
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}
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@ -313,13 +368,16 @@ bool TestParsers() {
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return true;
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}
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int main(int argc, const char *argv[])
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{
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int main(int argc, const char *argv[]) {
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cpu_info.bNEON = true;
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cpu_info.bVFP = true;
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cpu_info.bVFPv3 = true;
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cpu_info.bVFPv4 = true;
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g_Config.bEnableLogging = true;
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TestAsin();
|
||||
//TestAsin();
|
||||
//TestSinCos();
|
||||
//TestArmEmitter();
|
||||
TestMathUtil();
|
||||
TestParsers();
|
||||
TestArmEmitter();
|
||||
//TestMathUtil();
|
||||
//TestParsers();
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue