diff --git a/Core/MIPS/PPC/PpcAsm.cpp b/Core/MIPS/PPC/PpcAsm.cpp
index 309d817df5..0122cd060d 100644
--- a/Core/MIPS/PPC/PpcAsm.cpp
+++ b/Core/MIPS/PPC/PpcAsm.cpp
@@ -67,7 +67,7 @@ const u8 *Jit::DoJit(u32 em_address, JitBlock *b)
 	{
 		gpr.SetCompilerPC(js.compilerPC);  // Let it know for log messages
 		fpr.SetCompilerPC(js.compilerPC);
-		u32 inst = Memory::Read_Instruction(js.compilerPC);
+		MIPSOpcode inst = Memory::Read_Instruction(js.compilerPC);
 		js.downcountAmount += MIPSGetInstructionCycleEstimate(inst);
 
 		MIPSCompileOp(inst);
diff --git a/Core/MIPS/PPC/PpcCompAlu.cpp b/Core/MIPS/PPC/PpcCompAlu.cpp
index 2cd5845471..714f3924b5 100644
--- a/Core/MIPS/PPC/PpcCompAlu.cpp
+++ b/Core/MIPS/PPC/PpcCompAlu.cpp
@@ -77,7 +77,7 @@ namespace MIPSComp
 		}
 	}
 
-	void Jit::Comp_IType(u32 op)
+	void Jit::Comp_IType(MIPSOpcode op)
 	{
 		CONDITIONAL_DISABLE;
 		s32 simm = (s32)(s16)(op & 0xFFFF);  // sign extension
@@ -166,12 +166,12 @@ namespace MIPSComp
 		}
 	}
 
-	void Jit::Comp_RType2(u32 op) {
+	void Jit::Comp_RType2(MIPSOpcode op) {
 		Comp_Generic(op);
 	}
 
 
-	void Jit::Comp_RType3(u32 op) {
+	void Jit::Comp_RType3(MIPSOpcode op) {
 		CONDITIONAL_DISABLE;
 		int rt = _RT;
 		int rs = _RS;
@@ -364,7 +364,7 @@ namespace MIPSComp
 	/**
 	*	srl/srlv are disabled because they crash rr2
 	**/
-	void Jit::Comp_ShiftType(u32 op) {
+	void Jit::Comp_ShiftType(MIPSOpcode op) {
 		CONDITIONAL_DISABLE;
 		int rs = _RS;
 		int rd = _RD;
@@ -466,19 +466,19 @@ namespace MIPSComp
 		}
 	}
 
-	void Jit::Comp_Allegrex(u32 op) {
+	void Jit::Comp_Allegrex(MIPSOpcode op) {
 		Comp_Generic(op);
 	}
 
-	void Jit::Comp_Allegrex2(u32 op) {
+	void Jit::Comp_Allegrex2(MIPSOpcode op) {
 		Comp_Generic(op);
 	}
 
-	void Jit::Comp_MulDivType(u32 op) {
+	void Jit::Comp_MulDivType(MIPSOpcode op) {
 		Comp_Generic(op);
 	}
 
-	void Jit::Comp_Special3(u32 op) {
+	void Jit::Comp_Special3(MIPSOpcode op) {
 		Comp_Generic(op);
 	}
 
diff --git a/Core/MIPS/PPC/PpcCompBranch.cpp b/Core/MIPS/PPC/PpcCompBranch.cpp
index b594e1ab29..4533d4cbd0 100644
--- a/Core/MIPS/PPC/PpcCompBranch.cpp
+++ b/Core/MIPS/PPC/PpcCompBranch.cpp
@@ -16,14 +16,17 @@
 #include <ppcintrinsics.h>
 
 
-#define _RS ((op>>21) & 0x1F)
-#define _RT ((op>>16) & 0x1F)
-#define _RD ((op>>11) & 0x1F)
-#define _FS ((op>>11) & 0x1F)
-#define _FT ((op>>16) & 0x1F)
-#define _FD ((op>>6 ) & 0x1F)
-#define _POS  ((op>>6 ) & 0x1F)
-#define _SIZE ((op>>11 ) & 0x1F)
+#define _RS MIPS_GET_RS(op)
+#define _RT MIPS_GET_RT(op)
+#define _RD MIPS_GET_RD(op)
+#define _FS MIPS_GET_FS(op)
+#define _FT MIPS_GET_FT(op)
+#define _FD MIPS_GET_FD(op)
+#define _SA MIPS_GET_SA(op)
+#define _POS  ((op>> 6) & 0x1F)
+#define _SIZE ((op>>11) & 0x1F)
+#define _IMM16 (signed short)(op & 0xFFFF)
+#define _IMM26 (op & 0x03FFFFFF)
 
 #define LOOPOPTIMIZATION 0
 
@@ -42,18 +45,18 @@ using namespace PpcGen;
 namespace MIPSComp
 {
 	
-void Jit::BranchRSRTComp(u32 op, PpcGen::FixupBranchType cc, bool likely)
+void Jit::BranchRSRTComp(MIPSOpcode op, PpcGen::FixupBranchType cc, bool likely)
 {
 	if (js.inDelaySlot) {
 		ERROR_LOG_REPORT(JIT, "Branch in RSRTComp delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
 		return;
 	}
 	int offset = (signed short)(op&0xFFFF)<<2;
-	int rt = _RT;
-	int rs = _RS;
+	MIPSGPReg rt = _RT;
+	MIPSGPReg rs = _RS;
 	u32 targetAddr = js.compilerPC + offset + 4;
 		
-	u32 delaySlotOp = Memory::ReadUnchecked_U32(js.compilerPC+4);
+	MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC+4);
 	bool delaySlotIsNice = IsDelaySlotNiceReg(op, delaySlotOp, rt, rs);
 	CONDITIONAL_NICE_DELAYSLOT;
 	if (!likely && delaySlotIsNice)
@@ -104,17 +107,17 @@ void Jit::BranchRSRTComp(u32 op, PpcGen::FixupBranchType cc, bool likely)
 }
 
 
-void Jit::BranchRSZeroComp(u32 op, PpcGen::FixupBranchType cc, bool andLink, bool likely)
+void Jit::BranchRSZeroComp(MIPSOpcode op, PpcGen::FixupBranchType cc, bool andLink, bool likely)
 {
 	if (js.inDelaySlot) {
 		ERROR_LOG_REPORT(JIT, "Branch in RSZeroComp delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
 		return;
 	}
 	int offset = (signed short)(op&0xFFFF)<<2;
-	int rs = _RS;
+	MIPSGPReg rs = _RS;
 	u32 targetAddr = js.compilerPC + offset + 4;
 
-	u32 delaySlotOp = Memory::ReadUnchecked_U32(js.compilerPC + 4);
+	MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4);
 	bool delaySlotIsNice = IsDelaySlotNiceReg(op, delaySlotOp, rs);
 	CONDITIONAL_NICE_DELAYSLOT;
 	if (!likely && delaySlotIsNice)
@@ -156,7 +159,7 @@ void Jit::BranchRSZeroComp(u32 op, PpcGen::FixupBranchType cc, bool andLink, boo
 	js.compiling = false;
 }
 
-void Jit::Comp_RelBranch(u32 op) {
+void Jit::Comp_RelBranch(MIPSOpcode op) {
 	// The CC flags here should be opposite of the actual branch becuase they skip the branching action.
 	switch (op>>26) 
 	{
@@ -179,7 +182,7 @@ void Jit::Comp_RelBranch(u32 op) {
   js.compiling = false;
 }
 
-void Jit::Comp_RelBranchRI(u32 op) {
+void Jit::Comp_RelBranchRI(MIPSOpcode op) {
 	switch ((op >> 16) & 0x1F)
 	{
 	case 0: BranchRSZeroComp(op, _BGE, false, false); break; //if ((s32)R(rs) <  0) DelayBranchTo(addr); else PC += 4; break;//bltz
@@ -199,7 +202,7 @@ void Jit::Comp_RelBranchRI(u32 op) {
 
 
 // If likely is set, discard the branch slot if NOT taken.
-void Jit::BranchFPFlag(u32 op, PpcGen::FixupBranchType cc, bool likely)
+void Jit::BranchFPFlag(MIPSOpcode op, PpcGen::FixupBranchType cc, bool likely)
 {
 	if (js.inDelaySlot) {
 		ERROR_LOG_REPORT(JIT, "Branch in FPFlag delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
@@ -208,7 +211,7 @@ void Jit::BranchFPFlag(u32 op, PpcGen::FixupBranchType cc, bool likely)
 	int offset = (signed short)(op & 0xFFFF) << 2;
 	u32 targetAddr = js.compilerPC + offset + 4;
 
-	u32 delaySlotOp = Memory::ReadUnchecked_U32(js.compilerPC + 4);
+	MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4);
 	bool delaySlotIsNice = IsDelaySlotNiceFPU(op, delaySlotOp);
 	CONDITIONAL_NICE_DELAYSLOT;
 	if (!likely && delaySlotIsNice)
@@ -242,7 +245,7 @@ void Jit::BranchFPFlag(u32 op, PpcGen::FixupBranchType cc, bool likely)
 	js.compiling = false;
 }
 
-void Jit::Comp_FPUBranch(u32 op) {
+void Jit::Comp_FPUBranch(MIPSOpcode op) {
 	switch((op >> 16) & 0x1f)
 	{
 	case 0:	BranchFPFlag(op, _BNE, false); break;  // bc1f
@@ -258,7 +261,7 @@ void Jit::Comp_FPUBranch(u32 op) {
 
 
 // If likely is set, discard the branch slot if NOT taken.
-void Jit::BranchVFPUFlag(u32 op, PpcGen::FixupBranchType cc, bool likely)
+void Jit::BranchVFPUFlag(MIPSOpcode op, PpcGen::FixupBranchType cc, bool likely)
 {
 	if (js.inDelaySlot) {
 		ERROR_LOG_REPORT(JIT, "Branch in VFPU delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
@@ -267,7 +270,7 @@ void Jit::BranchVFPUFlag(u32 op, PpcGen::FixupBranchType cc, bool likely)
 	int offset = (signed short)(op & 0xFFFF) << 2;
 	u32 targetAddr = js.compilerPC + offset + 4;
 
-	u32 delaySlotOp = Memory::ReadUnchecked_U32(js.compilerPC + 4);
+	MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4);
 
 	bool delaySlotIsNice = IsDelaySlotNiceVFPU(op, delaySlotOp);
 	CONDITIONAL_NICE_DELAYSLOT;
@@ -309,7 +312,7 @@ void Jit::BranchVFPUFlag(u32 op, PpcGen::FixupBranchType cc, bool likely)
 	js.compiling = false;
 }
 
-void Jit::Comp_VBranch(u32 op) {
+void Jit::Comp_VBranch(MIPSOpcode op) {
 	switch ((op >> 16) & 3)
 	{
 	case 0:	BranchVFPUFlag(op, _BNE, false); break;  // bvf
@@ -320,7 +323,7 @@ void Jit::Comp_VBranch(u32 op) {
 	js.compiling = false;
 }
 
-void Jit::Comp_Jump(u32 op) {
+void Jit::Comp_Jump(MIPSOpcode op) {
 	if (js.inDelaySlot) {
 		ERROR_LOG_REPORT(JIT, "Branch in Jump delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
 		return;
@@ -351,14 +354,14 @@ void Jit::Comp_Jump(u32 op) {
 	js.compiling = false;
 }
 
-void Jit::Comp_JumpReg(u32 op) {
+void Jit::Comp_JumpReg(MIPSOpcode op) {
 	if (js.inDelaySlot) {
 		ERROR_LOG_REPORT(JIT, "Branch in JumpReg delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
 		return;
 	}
-	int rs = _RS;
+	MIPSGPReg rs = _RS;
 
-	u32 delaySlotOp = Memory::ReadUnchecked_U32(js.compilerPC + 4);
+	MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4);
 	bool delaySlotIsNice = IsDelaySlotNiceReg(op, delaySlotOp, rs);
 	CONDITIONAL_NICE_DELAYSLOT;
 
@@ -402,7 +405,7 @@ void Jit::Comp_JumpReg(u32 op) {
 	js.compiling = false;
 }
 
-void Jit::Comp_Syscall(u32 op) {
+void Jit::Comp_Syscall(MIPSOpcode op) {
 	FlushAll();
 
 	// If we're in a delay slot, this is off by one.
@@ -411,7 +414,7 @@ void Jit::Comp_Syscall(u32 op) {
 	js.downcountAmount = -offset;
 
 	// CallSyscall(op);
-	MOVI2R(R3, op);
+	MOVI2R(R3, op.encoding);
 	SaveDowncount(DCNTREG);
 	QuickCallFunction((void *)&CallSyscall);
 	RestoreDowncount(DCNTREG);
@@ -420,7 +423,7 @@ void Jit::Comp_Syscall(u32 op) {
 	js.compiling = false;
 }
 
-void Jit::Comp_Break(u32 op) {
+void Jit::Comp_Break(MIPSOpcode op) {
 	Comp_Generic(op);
 	WriteSyscallExit();
 	js.compiling = false;
diff --git a/Core/MIPS/PPC/PpcCompFpu.cpp b/Core/MIPS/PPC/PpcCompFpu.cpp
index 058678713d..0d849760d3 100644
--- a/Core/MIPS/PPC/PpcCompFpu.cpp
+++ b/Core/MIPS/PPC/PpcCompFpu.cpp
@@ -31,7 +31,7 @@ using namespace PpcGen;
 namespace MIPSComp
 {
 	
-void Jit::Comp_FPU3op(u32 op) {
+void Jit::Comp_FPU3op(MIPSOpcode op) {
 	CONDITIONAL_DISABLE;
 
 	int ft = _FT;
@@ -68,7 +68,7 @@ void Jit::Comp_FPU3op(u32 op) {
 	}
 }
 
-void Jit::Comp_FPULS(u32 op) {
+void Jit::Comp_FPULS(MIPSOpcode op) {
 	CONDITIONAL_DISABLE;
 
 	s32 offset = (s16)(op & 0xFFFF);
@@ -116,11 +116,11 @@ void Jit::Comp_FPULS(u32 op) {
 	}
 }
 
-void Jit::Comp_FPUComp(u32 op) {
+void Jit::Comp_FPUComp(MIPSOpcode op) {
 	Comp_Generic(op);
 }
 
-void Jit::Comp_FPU2op(u32 op) {
+void Jit::Comp_FPU2op(MIPSOpcode op) {
 	CONDITIONAL_DISABLE;
 
 	int fs = _FS;
@@ -150,7 +150,7 @@ void Jit::Comp_FPU2op(u32 op) {
 	}
 }
 
-void Jit::Comp_mxc1(u32 op) {
+void Jit::Comp_mxc1(MIPSOpcode op) {
 	Comp_Generic(op);
 }
 
diff --git a/Core/MIPS/PPC/PpcCompLoadStore.cpp b/Core/MIPS/PPC/PpcCompLoadStore.cpp
index 936d51135b..6f266cfb8e 100644
--- a/Core/MIPS/PPC/PpcCompLoadStore.cpp
+++ b/Core/MIPS/PPC/PpcCompLoadStore.cpp
@@ -41,7 +41,7 @@ void Jit::SetRegToEffectiveAddress(PpcGen::PPCReg r, int rs, s16 offset) {
 	}
 		
 }
-void Jit::Comp_ITypeMem(u32 op) {
+void Jit::Comp_ITypeMem(MIPSOpcode op) {
 	CONDITIONAL_DISABLE;
 		int offset = (signed short)(op&0xFFFF);
 		bool load = false;
@@ -120,13 +120,13 @@ void Jit::Comp_ITypeMem(u32 op) {
 			if (!js.inDelaySlot) {
 				// Optimisation: Combine to single unaligned load/store
 				bool isLeft = (o == 34 || o == 42);
-				u32 nextOp = Memory::Read_Instruction(js.compilerPC + 4);
+				MIPSOpcode nextOp = Memory::Read_Instruction(js.compilerPC + 4);
 				// Find a matching shift in opposite direction with opposite offset.
-				if (nextOp == (isLeft ? (op + (4<<26) - 3)
-				                      : (op - (4<<26) + 3)))
+				if (nextOp == (isLeft ? (op.encoding + (4<<26) - 3)
+				                      : (op.encoding - (4<<26) + 3)))
 				{
 					EatInstruction(nextOp);
-					nextOp = ((load ? 35 : 43) << 26) | ((isLeft ? nextOp : op) & 0x3FFFFFF); //lw, sw
+					nextOp = MIPSOpcode(((load ? 35 : 43) << 26) | ((isLeft ? nextOp : op) & 0x03FFFFFF)); //lw, sw
 					Comp_ITypeMem(nextOp);
 					return;
 				}
diff --git a/Core/MIPS/PPC/PpcCompVFPU.cpp b/Core/MIPS/PPC/PpcCompVFPU.cpp
index 73d9584c98..3d47af2bba 100644
--- a/Core/MIPS/PPC/PpcCompVFPU.cpp
+++ b/Core/MIPS/PPC/PpcCompVFPU.cpp
@@ -57,7 +57,7 @@ namespace MIPSComp
 		return IsOverlapSafeAllowS(dreg, di, sn, sregs, tn, tregs) && sregs[di] != dreg;
 	}
 
-	void Jit::Comp_SV(u32 op) {
+	void Jit::Comp_SV(MIPSOpcode op) {
 		CONDITIONAL_DISABLE;
 
 		s32 imm = (signed short)(op&0xFFFC);
@@ -104,7 +104,7 @@ namespace MIPSComp
 		}
 	}
 
-	void Jit::Comp_SVQ(u32 op) {
+	void Jit::Comp_SVQ(MIPSOpcode op) {
 		// Comp_Generic(op);
 		CONDITIONAL_DISABLE;
 
@@ -167,125 +167,125 @@ namespace MIPSComp
 		fpr.ReleaseSpillLocksAndDiscardTemps();
 	}
 
-	void Jit::Comp_VPFX(u32 op) {
+	void Jit::Comp_VPFX(MIPSOpcode op) {
 		Comp_Generic(op);
 	}
 
-	void Jit::Comp_VVectorInit(u32 op) {
+	void Jit::Comp_VVectorInit(MIPSOpcode op) {
 		Comp_Generic(op);
 	}
 
-	void Jit::Comp_VMatrixInit(u32 op) {
+	void Jit::Comp_VMatrixInit(MIPSOpcode op) {
 		Comp_Generic(op);
 	}
 
-	void Jit::Comp_VDot(u32 op) {
+	void Jit::Comp_VDot(MIPSOpcode op) {
 		Comp_Generic(op);
 	}
 
-	void Jit::Comp_VecDo3(u32 op) {
+	void Jit::Comp_VecDo3(MIPSOpcode op) {
 		Comp_Generic(op);
 	}
 
-	void Jit::Comp_VV2Op(u32 op) {
+	void Jit::Comp_VV2Op(MIPSOpcode op) {
 		Comp_Generic(op);
 	}
 
-	void Jit::Comp_Mftv(u32 op) {
+	void Jit::Comp_Mftv(MIPSOpcode op) {
 		Comp_Generic(op);
 	}
 
-	void Jit::Comp_Vmtvc(u32 op) {
+	void Jit::Comp_Vmtvc(MIPSOpcode op) {
 		Comp_Generic(op);
 	}
 
-	void Jit::Comp_Vmmov(u32 op) {
+	void Jit::Comp_Vmmov(MIPSOpcode op) {
 		Comp_Generic(op);
 	}
 
-	void Jit::Comp_VScl(u32 op) {
+	void Jit::Comp_VScl(MIPSOpcode op) {
 		Comp_Generic(op);
 	}
 
-	void Jit::Comp_Vmmul(u32 op) {
+	void Jit::Comp_Vmmul(MIPSOpcode op) {
 		Comp_Generic(op);
 	}
 
-	void Jit::Comp_Vmscl(u32 op) {
+	void Jit::Comp_Vmscl(MIPSOpcode op) {
 		Comp_Generic(op);
 	}
 
-	void Jit::Comp_Vtfm(u32 op) {
+	void Jit::Comp_Vtfm(MIPSOpcode op) {
 		Comp_Generic(op);
 	}
 
-	void Jit::Comp_VHdp(u32 op) {
+	void Jit::Comp_VHdp(MIPSOpcode op) {
 		Comp_Generic(op);
 	}
 
-	void Jit::Comp_VCrs(u32 op) {
+	void Jit::Comp_VCrs(MIPSOpcode op) {
 		Comp_Generic(op);
 	}
 
-	void Jit::Comp_VDet(u32 op) {
+	void Jit::Comp_VDet(MIPSOpcode op) {
 		Comp_Generic(op);
 	}
 
-	void Jit::Comp_Vi2x(u32 op) {
+	void Jit::Comp_Vi2x(MIPSOpcode op) {
 		Comp_Generic(op);
 	}
 
-	void Jit::Comp_Vx2i(u32 op) {
+	void Jit::Comp_Vx2i(MIPSOpcode op) {
 		Comp_Generic(op);
 	}
 
-	void Jit::Comp_Vf2i(u32 op) {
+	void Jit::Comp_Vf2i(MIPSOpcode op) {
 		Comp_Generic(op);
 	}
 
-	void Jit::Comp_Vi2f(u32 op) {
+	void Jit::Comp_Vi2f(MIPSOpcode op) {
 		Comp_Generic(op);
 	}
 
-	void Jit::Comp_Vcst(u32 op) {
+	void Jit::Comp_Vcst(MIPSOpcode op) {
 		Comp_Generic(op);
 	}
 
-	void Jit::Comp_Vhoriz(u32 op) {
+	void Jit::Comp_Vhoriz(MIPSOpcode op) {
 		Comp_Generic(op);
 	}
 
-	void Jit::Comp_VRot(u32 op) {
+	void Jit::Comp_VRot(MIPSOpcode op) {
 		Comp_Generic(op);
 	}
 
-	void Jit::Comp_VIdt(u32 op) {
+	void Jit::Comp_VIdt(MIPSOpcode op) {
 		Comp_Generic(op);
 	}
 
-	void Jit::Comp_Vcmp(u32 op) {
+	void Jit::Comp_Vcmp(MIPSOpcode op) {
 		Comp_Generic(op);
 	}
 
-	void Jit::Comp_Vcmov(u32 op) {
+	void Jit::Comp_Vcmov(MIPSOpcode op) {
 		Comp_Generic(op);
 	}
 
-	void Jit::Comp_Viim(u32 op) {
+	void Jit::Comp_Viim(MIPSOpcode op) {
 		Comp_Generic(op);
 	}
 
-	void Jit::Comp_Vfim(u32 op) {
+	void Jit::Comp_Vfim(MIPSOpcode op) {
 		Comp_Generic(op);
 	}
 
-	void Jit::Comp_VCrossQuat(u32 op) {
+	void Jit::Comp_VCrossQuat(MIPSOpcode op) {
 		Comp_Generic(op);
 	}
-	void Jit::Comp_Vsge(u32 op) {
+	void Jit::Comp_Vsge(MIPSOpcode op) {
 		Comp_Generic(op);
 	}
-	void Jit::Comp_Vslt(u32 op) {
+	void Jit::Comp_Vslt(MIPSOpcode op) {
 		Comp_Generic(op);
 	}
 }
\ No newline at end of file
diff --git a/Core/MIPS/PPC/PpcJit.cpp b/Core/MIPS/PPC/PpcJit.cpp
index d89552de60..f9ece053da 100644
--- a/Core/MIPS/PPC/PpcJit.cpp
+++ b/Core/MIPS/PPC/PpcJit.cpp
@@ -35,7 +35,7 @@ void Jit::CompileDelaySlot(int flags)
 	}
 
 	js.inDelaySlot = true;
-	u32 op = Memory::Read_Instruction(js.compilerPC + 4);
+	MIPSOpcode op = Memory::Read_Instruction(js.compilerPC + 4);
 	MIPSCompileOp(op);
 	js.inDelaySlot = false;
 
@@ -119,7 +119,7 @@ void Jit::WriteDownCount(int offset)
 	CMPI(DCNTREG, 0);
 }
 
-void Jit::Comp_Generic(u32 op) {
+void Jit::Comp_Generic(MIPSOpcode op) {
 	FlushAll();
 
 	// basic jit !!
@@ -132,19 +132,23 @@ void Jit::Comp_Generic(u32 op) {
 		MovToPC(SREG);
 
 		// call interpreted function
-		MOVI2R(R3, op);
+		MOVI2R(R3, op.encoding);
 		QuickCallFunction((void *)func);
 
 		// restore pc and cycles
 		RestoreDowncount(DCNTREG);
 	}
-	// Might have eaten prefixes, hard to tell...
-	if ((MIPSGetInfo(op) & IS_VFPU) != 0)
-		js.PrefixStart();
+	const MIPSInfo info = MIPSGetInfo(op);
+	if ((info & IS_VFPU) != 0 && (info & VFPU_NO_PREFIX) == 0)
+	{
+		// If it does eat them, it'll happen in MIPSCompileOp().
+		if ((info & OUT_EAT_PREFIX) == 0)
+			js.PrefixUnknown();
+	}
 }
 	
-void Jit::EatInstruction(u32 op) {
-	u32 info = MIPSGetInfo(op);
+void Jit::EatInstruction(MIPSOpcode op) {
+	MIPSInfo info = MIPSGetInfo(op);
 	_dbg_assert_msg_(JIT, !(info & DELAYSLOT), "Never eat a branch op.");
 	_dbg_assert_msg_(JIT, !js.inDelaySlot, "Never eat an instruction inside a delayslot.");
 
@@ -152,12 +156,12 @@ void Jit::EatInstruction(u32 op) {
 	js.downcountAmount += MIPSGetInstructionCycleEstimate(op);
 }
 
-void Jit::Comp_RunBlock(u32 op) {
+void Jit::Comp_RunBlock(MIPSOpcode op) {
 	// This shouldn't be necessary, the dispatcher should catch us before we get here.
 	ERROR_LOG(JIT, "Comp_RunBlock should never be reached!");
 }
 
-void Jit::Comp_DoNothing(u32 op) {
+void Jit::Comp_DoNothing(MIPSOpcode op) {
 
 }
 
diff --git a/Core/MIPS/PPC/PpcJit.h b/Core/MIPS/PPC/PpcJit.h
index 400bb8fe53..d2a96e2bba 100644
--- a/Core/MIPS/PPC/PpcJit.h
+++ b/Core/MIPS/PPC/PpcJit.h
@@ -153,83 +153,83 @@ namespace MIPSComp
 		// Compiled ops should ignore delay slots
 		// the compiler will take care of them by itself
 		// OR NOT
-		void Comp_Generic(u32 op);
+		void Comp_Generic(MIPSOpcode op);
 
-		void EatInstruction(u32 op);
-		void Comp_RunBlock(u32 op);
+		void EatInstruction(MIPSOpcode op);
+		void Comp_RunBlock(MIPSOpcode op);
 
 		// TODO: Eat VFPU prefixes here.
 		void EatPrefix() { js.EatPrefix(); }
 
 		// Ops
-		void Comp_ITypeMem(u32 op);
+		void Comp_ITypeMem(MIPSOpcode op);
 
-		void Comp_RelBranch(u32 op);
-		void Comp_RelBranchRI(u32 op);
-		void Comp_FPUBranch(u32 op);
-		void Comp_FPULS(u32 op);
-		void Comp_FPUComp(u32 op);
-		void Comp_Jump(u32 op);
-		void Comp_JumpReg(u32 op);
-		void Comp_Syscall(u32 op);
-		void Comp_Break(u32 op);
+		void Comp_RelBranch(MIPSOpcode op);
+		void Comp_RelBranchRI(MIPSOpcode op);
+		void Comp_FPUBranch(MIPSOpcode op);
+		void Comp_FPULS(MIPSOpcode op);
+		void Comp_FPUComp(MIPSOpcode op);
+		void Comp_Jump(MIPSOpcode op);
+		void Comp_JumpReg(MIPSOpcode op);
+		void Comp_Syscall(MIPSOpcode op);
+		void Comp_Break(MIPSOpcode op);
 
-		void Comp_IType(u32 op);
-		void Comp_RType2(u32 op);
-		void Comp_RType3(u32 op);
-		void Comp_ShiftType(u32 op);
-		void Comp_Allegrex(u32 op);
-		void Comp_Allegrex2(u32 op);
-		void Comp_VBranch(u32 op);
-		void Comp_MulDivType(u32 op);
-		void Comp_Special3(u32 op);
+		void Comp_IType(MIPSOpcode op);
+		void Comp_RType2(MIPSOpcode op);
+		void Comp_RType3(MIPSOpcode op);
+		void Comp_ShiftType(MIPSOpcode op);
+		void Comp_Allegrex(MIPSOpcode op);
+		void Comp_Allegrex2(MIPSOpcode op);
+		void Comp_VBranch(MIPSOpcode op);
+		void Comp_MulDivType(MIPSOpcode op);
+		void Comp_Special3(MIPSOpcode op);
 
-		void Comp_FPU3op(u32 op);
-		void Comp_FPU2op(u32 op);
-		void Comp_mxc1(u32 op);
+		void Comp_FPU3op(MIPSOpcode op);
+		void Comp_FPU2op(MIPSOpcode op);
+		void Comp_mxc1(MIPSOpcode op);
 
-		void Comp_DoNothing(u32 op);
+		void Comp_DoNothing(MIPSOpcode op);
 
-		void Comp_SV(u32 op);
-		void Comp_SVQ(u32 op);
-		void Comp_VPFX(u32 op);
-		void Comp_VVectorInit(u32 op);	
-		void Comp_VMatrixInit(u32 op);
-		void Comp_VDot(u32 op);
-		void Comp_VecDo3(u32 op);
-		void Comp_VV2Op(u32 op);
-		void Comp_Mftv(u32 op);
-		void Comp_Vmtvc(u32 op);
-		void Comp_Vmmov(u32 op);
-		void Comp_VScl(u32 op);
-		void Comp_Vmmul(u32 op);
-		void Comp_Vmscl(u32 op);
-		void Comp_Vtfm(u32 op);
-		void Comp_VHdp(u32 op);
-		void Comp_VCrs(u32 op);
-		void Comp_VDet(u32 op);
-		void Comp_Vi2x(u32 op);
-		void Comp_Vx2i(u32 op);
-		void Comp_Vf2i(u32 op);
-		void Comp_Vi2f(u32 op);
-		void Comp_Vcst(u32 op);
-		void Comp_Vhoriz(u32 op);	
-		void Comp_VRot(u32 op);
-		void Comp_VIdt(u32 op);
-		void Comp_Vcmp(u32 op);
-		void Comp_Vcmov(u32 op);
-		void Comp_Viim(u32 op);
-		void Comp_Vfim(u32 op);
-		void Comp_VCrossQuat(u32 op);
-		void Comp_Vsge(u32 op);
-		void Comp_Vslt(u32 op);
+		void Comp_SV(MIPSOpcode op);
+		void Comp_SVQ(MIPSOpcode op);
+		void Comp_VPFX(MIPSOpcode op);
+		void Comp_VVectorInit(MIPSOpcode op);	
+		void Comp_VMatrixInit(MIPSOpcode op);
+		void Comp_VDot(MIPSOpcode op);
+		void Comp_VecDo3(MIPSOpcode op);
+		void Comp_VV2Op(MIPSOpcode op);
+		void Comp_Mftv(MIPSOpcode op);
+		void Comp_Vmtvc(MIPSOpcode op);
+		void Comp_Vmmov(MIPSOpcode op);
+		void Comp_VScl(MIPSOpcode op);
+		void Comp_Vmmul(MIPSOpcode op);
+		void Comp_Vmscl(MIPSOpcode op);
+		void Comp_Vtfm(MIPSOpcode op);
+		void Comp_VHdp(MIPSOpcode op);
+		void Comp_VCrs(MIPSOpcode op);
+		void Comp_VDet(MIPSOpcode op);
+		void Comp_Vi2x(MIPSOpcode op);
+		void Comp_Vx2i(MIPSOpcode op);
+		void Comp_Vf2i(MIPSOpcode op);
+		void Comp_Vi2f(MIPSOpcode op);
+		void Comp_Vcst(MIPSOpcode op);
+		void Comp_Vhoriz(MIPSOpcode op);	
+		void Comp_VRot(MIPSOpcode op);
+		void Comp_VIdt(MIPSOpcode op);
+		void Comp_Vcmp(MIPSOpcode op);
+		void Comp_Vcmov(MIPSOpcode op);
+		void Comp_Viim(MIPSOpcode op);
+		void Comp_Vfim(MIPSOpcode op);
+		void Comp_VCrossQuat(MIPSOpcode op);
+		void Comp_Vsge(MIPSOpcode op);
+		void Comp_Vslt(MIPSOpcode op);
 
 
 		// Utility compilation functions
-		void BranchFPFlag(u32 op, PpcGen::FixupBranchType cc, bool likely);
-		void BranchVFPUFlag(u32 op, PpcGen::FixupBranchType cc, bool likely);
-		void BranchRSZeroComp(u32 op, PpcGen::FixupBranchType cc, bool andLink, bool likely);
-		void BranchRSRTComp(u32 op, PpcGen::FixupBranchType cc, bool likely);
+		void BranchFPFlag(MIPSOpcode op, PpcGen::FixupBranchType cc, bool likely);
+		void BranchVFPUFlag(MIPSOpcode op, PpcGen::FixupBranchType cc, bool likely);
+		void BranchRSZeroComp(MIPSOpcode op, PpcGen::FixupBranchType cc, bool andLink, bool likely);
+		void BranchRSRTComp(MIPSOpcode op, PpcGen::FixupBranchType cc, bool likely);
 
 		void SetRegToEffectiveAddress(PpcGen::PPCReg r, int rs, s16 offset);
 		
@@ -288,8 +288,8 @@ namespace MIPSComp
 			const u8 *breakpointBailout;
 
 	};
-
-	typedef void (Jit::*MIPSCompileFunc)(u32 opcode);
+	
+	typedef void (Jit::*MIPSCompileFunc)(MIPSOpcode opcode);
 
 }	// namespace MIPSComp