mirror of
https://github.com/hrydgard/ppsspp.git
synced 2025-04-02 11:01:50 -04:00
x86jit: Refactor and skip flushes in branch cont.
Still not faster, but at least the code isn't as messy.
This commit is contained in:
Unknown W. Brackets
parent
32504ed46e
commit
a334aaf6ca
2 changed files with 105 additions and 266 deletions
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@ -165,6 +165,106 @@ bool Jit::PredictTakeBranch(u32 targetAddr, bool likely) {
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return targetAddr > js.compilerPC;
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}
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void Jit::CompBranchExits(CCFlags cc, u32 targetAddr, u32 notTakenAddr, bool delaySlotIsNice, bool likely, bool andLink) {
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// We may want to try to continue along this branch a little while, to reduce reg flushing.
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if (CanContinueBranch())
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{
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bool predictTakeBranch = PredictTakeBranch(targetAddr, likely);
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if (predictTakeBranch)
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cc = FlipCCFlag(cc);
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Gen::FixupBranch ptr;
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RegCacheState state;
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if (!likely)
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{
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if (!delaySlotIsNice)
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CompileDelaySlot(DELAYSLOT_SAFE);
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ptr = J_CC(cc, true);
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GetStateAndFlushAll(state);
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}
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else
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{
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ptr = J_CC(cc, true);
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if (predictTakeBranch)
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GetStateAndFlushAll(state);
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else
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CompileDelaySlot(DELAYSLOT_FLUSH);
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}
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if (predictTakeBranch)
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{
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// We flipped the cc, the not taken case is first.
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CONDITIONAL_LOG_EXIT(notTakenAddr);
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WriteExit(notTakenAddr, js.nextExit++);
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// Now our taken path. Bring the regs back, we didn't flush 'em after all.
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SetJumpTarget(ptr);
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RestoreState(state);
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CONDITIONAL_LOG_EXIT(targetAddr);
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if (andLink)
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gpr.SetImm(MIPS_REG_RA, js.compilerPC + 8);
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// Don't forget to run the delay slot if likely.
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if (likely)
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CompileDelaySlot(DELAYSLOT_NICE);
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// Account for the increment in the loop.
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js.compilerPC = targetAddr - 4;
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// In case the delay slot was a break or something.
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js.compiling = true;
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}
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else
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{
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// Take the branch
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if (andLink)
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MOV(32, M(&mips_->r[MIPS_REG_RA]), Imm32(js.compilerPC + 8));
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CONDITIONAL_LOG_EXIT(targetAddr);
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WriteExit(targetAddr, js.nextExit++);
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// Not taken
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SetJumpTarget(ptr);
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RestoreState(state);
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CONDITIONAL_LOG_EXIT(notTakenAddr);
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// Account for the delay slot.
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js.compilerPC += 4;
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// In case the delay slot was a break or something.
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js.compiling = true;
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}
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}
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else
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{
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Gen::FixupBranch ptr;
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if (!likely)
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{
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if (!delaySlotIsNice)
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CompileDelaySlot(DELAYSLOT_SAFE_FLUSH);
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else
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FlushAll();
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ptr = J_CC(cc, true);
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}
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else
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{
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FlushAll();
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ptr = J_CC(cc, true);
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CompileDelaySlot(DELAYSLOT_FLUSH);
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}
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// Take the branch
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if (andLink)
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MOV(32, M(&mips_->r[MIPS_REG_RA]), Imm32(js.compilerPC + 8));
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CONDITIONAL_LOG_EXIT(targetAddr);
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WriteExit(targetAddr, js.nextExit++);
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// Not taken
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SetJumpTarget(ptr);
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CONDITIONAL_LOG_EXIT(notTakenAddr);
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WriteExit(notTakenAddr, js.nextExit++);
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js.compiling = false;
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}
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}
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void Jit::BranchRSRTComp(MIPSOpcode op, Gen::CCFlags cc, bool likely)
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{
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CONDITIONAL_LOG;
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@ -225,71 +325,7 @@ void Jit::BranchRSRTComp(MIPSOpcode op, Gen::CCFlags cc, bool likely)
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CMP(32, gpr.R(rs), gpr.R(rt));
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}
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// We may want to try to continue along this branch a little while, to reduce reg flushing.
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bool predictTakeBranch = PredictTakeBranch(targetAddr, likely);
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bool continueBranch = false;
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// Likely delay slots may change regs, can't take those branches inline safely.
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if (CanContinueBranch() && (!likely || !predictTakeBranch))
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{
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continueBranch = true;
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if (predictTakeBranch)
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cc = FlipCCFlag(cc);
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}
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Gen::FixupBranch ptr;
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RegCacheState state;
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if (!likely)
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{
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if (!delaySlotIsNice)
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CompileDelaySlot(DELAYSLOT_SAFE_FLUSH, state);
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else
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GetStateAndFlushAll(state);
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ptr = J_CC(cc, true);
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}
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else
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{
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GetStateAndFlushAll(state);
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ptr = J_CC(cc, true);
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CompileDelaySlot(DELAYSLOT_FLUSH);
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}
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if (continueBranch && predictTakeBranch)
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{
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// We flipped the cc, the not taken case is first.
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CONDITIONAL_LOG_EXIT(js.compilerPC + 8);
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WriteExit(js.compilerPC + 8, js.nextExit++);
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// Now our taken path.
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SetJumpTarget(ptr);
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CONDITIONAL_LOG_EXIT(targetAddr);
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// Account for the increment in the loop.
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js.compilerPC = targetAddr - 4;
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// In case the delay slot was a break or something.
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js.compiling = true;
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return;
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}
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// Take the branch
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CONDITIONAL_LOG_EXIT(targetAddr);
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WriteExit(targetAddr, js.nextExit++);
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// Not taken
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SetJumpTarget(ptr);
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CONDITIONAL_LOG_EXIT(js.compilerPC + 8);
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if (continueBranch && !predictTakeBranch)
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{
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// Account for the delay slot.
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js.compilerPC += 4;
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RestoreState(state);
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// In case the delay slot was a break or something.
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js.compiling = true;
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}
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else
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{
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WriteExit(js.compilerPC + 8, js.nextExit++);
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js.compiling = false;
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}
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CompBranchExits(cc, targetAddr, js.compilerPC + 8, delaySlotIsNice, likely, false);
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}
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void Jit::BranchRSZeroComp(MIPSOpcode op, Gen::CCFlags cc, bool andLink, bool likely)
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@ -347,75 +383,7 @@ void Jit::BranchRSZeroComp(MIPSOpcode op, Gen::CCFlags cc, bool andLink, bool li
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gpr.MapReg(rs, true, false);
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CMP(32, gpr.R(rs), Imm32(0));
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// We may want to try to continue along this branch a little while, to reduce reg flushing.
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bool predictTakeBranch = PredictTakeBranch(targetAddr, likely);
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bool continueBranch = false;
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// Likely delay slots may change regs, can't take those branches inline safely.
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if (CanContinueBranch() && (!likely || !predictTakeBranch))
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{
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continueBranch = true;
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if (predictTakeBranch)
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cc = FlipCCFlag(cc);
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}
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Gen::FixupBranch ptr;
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RegCacheState state;
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if (!likely)
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{
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if (!delaySlotIsNice)
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CompileDelaySlot(DELAYSLOT_SAFE_FLUSH, state);
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else
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GetStateAndFlushAll(state);
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ptr = J_CC(cc, true);
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}
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else
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{
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GetStateAndFlushAll(state);
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ptr = J_CC(cc, true);
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CompileDelaySlot(DELAYSLOT_FLUSH);
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}
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if (continueBranch && predictTakeBranch)
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{
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// We flipped the cc, the not taken case is first.
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CONDITIONAL_LOG_EXIT(js.compilerPC + 8);
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WriteExit(js.compilerPC + 8, js.nextExit++);
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// Now our taken path.
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SetJumpTarget(ptr);
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if (andLink)
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gpr.SetImm(MIPS_REG_RA, js.compilerPC + 8);
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CONDITIONAL_LOG_EXIT(targetAddr);
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// Account for the increment in the loop.
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js.compilerPC = targetAddr - 4;
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// In case the delay slot was a break or something.
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js.compiling = true;
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return;
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}
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// Take the branch
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if (andLink)
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MOV(32, M(&mips_->r[MIPS_REG_RA]), Imm32(js.compilerPC + 8));
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CONDITIONAL_LOG_EXIT(targetAddr);
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WriteExit(targetAddr, js.nextExit++);
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// Not taken
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SetJumpTarget(ptr);
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CONDITIONAL_LOG_EXIT(js.compilerPC + 8);
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if (continueBranch && !predictTakeBranch)
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{
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// Account for the delay slot.
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js.compilerPC += 4;
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RestoreState(state);
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// In case the delay slot was a break or something.
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js.compiling = true;
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}
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else
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{
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WriteExit(js.compilerPC + 8, js.nextExit++);
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js.compiling = false;
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}
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CompBranchExits(cc, targetAddr, js.compilerPC + 8, delaySlotIsNice, likely, andLink);
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}
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@ -477,72 +445,9 @@ void Jit::BranchFPFlag(MIPSOpcode op, Gen::CCFlags cc, bool likely)
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if (!likely && delaySlotIsNice)
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CompileDelaySlot(DELAYSLOT_NICE);
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// We may want to try to continue along this branch a little while, to reduce reg flushing.
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bool predictTakeBranch = PredictTakeBranch(targetAddr, likely);
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bool continueBranch = false;
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// Likely delay slots may change regs, can't take those branches inline safely.
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if (CanContinueBranch() && (!likely || !predictTakeBranch))
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{
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continueBranch = true;
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if (predictTakeBranch)
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cc = FlipCCFlag(cc);
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}
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TEST(32, M((void *)&(mips_->fpcond)), Imm32(1));
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Gen::FixupBranch ptr;
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RegCacheState state;
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if (!likely)
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{
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if (!delaySlotIsNice)
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CompileDelaySlot(DELAYSLOT_SAFE_FLUSH, state);
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else
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GetStateAndFlushAll(state);
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ptr = J_CC(cc, true);
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}
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else
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{
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GetStateAndFlushAll(state);
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ptr = J_CC(cc, true);
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CompileDelaySlot(DELAYSLOT_FLUSH);
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}
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if (continueBranch && predictTakeBranch)
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{
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// We flipped the cc, the not taken case is first.
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CONDITIONAL_LOG_EXIT(js.compilerPC + 8);
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WriteExit(js.compilerPC + 8, js.nextExit++);
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// Now our taken path.
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SetJumpTarget(ptr);
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CONDITIONAL_LOG_EXIT(targetAddr);
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// Account for the increment in the loop.
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js.compilerPC = targetAddr - 4;
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// In case the delay slot was a break or something.
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js.compiling = true;
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return;
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}
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// Take the branch
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CONDITIONAL_LOG_EXIT(targetAddr);
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WriteExit(targetAddr, js.nextExit++);
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// Not taken
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SetJumpTarget(ptr);
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CONDITIONAL_LOG_EXIT(js.compilerPC + 8);
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if (continueBranch && !predictTakeBranch)
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{
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// Account for the delay slot.
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js.compilerPC += 4;
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RestoreState(state);
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// In case the delay slot was a break or something.
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js.compiling = true;
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}
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else
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{
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WriteExit(js.compilerPC + 8, js.nextExit++);
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js.compiling = false;
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}
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CompBranchExits(cc, targetAddr, js.compilerPC + 8, delaySlotIsNice, likely, false);
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}
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@ -584,81 +489,14 @@ void Jit::BranchVFPUFlag(MIPSOpcode op, Gen::CCFlags cc, bool likely)
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if (delaySlotIsBranch && (signed short)(delaySlotOp & 0xFFFF) != (signed short)(op & 0xFFFF) - 1)
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ERROR_LOG_REPORT(JIT, "VFPU branch in VFPU delay slot at %08x with different target %d / %d", js.compilerPC, (signed short)(delaySlotOp & 0xFFFF), (signed short)(op & 0xFFFF) - 1);
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// We may want to try to continue along this branch a little while, to reduce reg flushing.
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bool predictTakeBranch = PredictTakeBranch(targetAddr, likely);
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bool continueBranch = false;
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// Likely delay slots may change regs, can't take those branches inline safely.
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// TODO: Maybe delaySlotIsBranch could work, but let's play it safe.
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if (CanContinueBranch() && (!likely || !predictTakeBranch) && !delaySlotIsBranch)
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{
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continueBranch = true;
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if (predictTakeBranch)
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cc = FlipCCFlag(cc);
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}
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// THE CONDITION
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int imm3 = (op >> 18) & 7;
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//int val = (mips_->vfpuCtrl[VFPU_CTRL_CC] >> imm3) & 1;
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TEST(32, M((void *)&(mips_->vfpuCtrl[VFPU_CTRL_CC])), Imm32(1 << imm3));
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Gen::FixupBranch ptr;
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RegCacheState state;
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if (!likely)
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{
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if (!delaySlotIsNice && !delaySlotIsBranch)
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CompileDelaySlot(DELAYSLOT_SAFE_FLUSH, state);
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else
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GetStateAndFlushAll(state);
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ptr = J_CC(cc, true);
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}
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else
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{
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GetStateAndFlushAll(state);
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ptr = J_CC(cc, true);
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if (!delaySlotIsBranch)
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CompileDelaySlot(DELAYSLOT_FLUSH);
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}
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u32 notTakenTarget = js.compilerPC + (delaySlotIsBranch ? 4 : 8);
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if (continueBranch && predictTakeBranch)
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{
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// We flipped the cc, the not taken case is first.
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CONDITIONAL_LOG_EXIT(notTakenTarget);
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WriteExit(notTakenTarget, js.nextExit++);
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// Now our taken path.
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SetJumpTarget(ptr);
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CONDITIONAL_LOG_EXIT(targetAddr);
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// Account for the increment in the loop.
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js.compilerPC = targetAddr - 4;
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// In case the delay slot was a break or something.
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js.compiling = true;
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return;
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}
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// Take the branch
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CONDITIONAL_LOG_EXIT(targetAddr);
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WriteExit(targetAddr, js.nextExit++);
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// Not taken
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SetJumpTarget(ptr);
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CONDITIONAL_LOG_EXIT(notTakenTarget);
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if (continueBranch && !predictTakeBranch)
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{
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// Account for the delay slot.
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if (!delaySlotIsBranch)
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js.compilerPC += 4;
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RestoreState(state);
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// In case the delay slot was a break or something.
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js.compiling = true;
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}
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else
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{
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WriteExit(notTakenTarget, js.nextExit++);
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js.compiling = false;
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}
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CompBranchExits(cc, targetAddr, notTakenTarget, delaySlotIsNice, likely, false);
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}
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@ -196,6 +196,7 @@ private:
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void CompITypeMemWrite(MIPSOpcode op, u32 bits, void *safeFunc);
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void CompITypeMemUnpairedLR(MIPSOpcode op, bool isStore);
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void CompITypeMemUnpairedLRInner(MIPSOpcode op, X64Reg shiftReg);
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void CompBranchExits(CCFlags cc, u32 targetAddr, u32 notTakenAddr, bool delaySlotIsNice, bool likely, bool andLink);
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void CompFPTriArith(MIPSOpcode op, void (XEmitter::*arith)(X64Reg reg, OpArg), bool orderMatters);
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void CompFPComp(int lhs, int rhs, u8 compare, bool allowNaN = false);
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