From a26b48fc0b7fc3c193b2ccc00af4cd834cb276cd Mon Sep 17 00:00:00 2001
From: Sacha <xsacha@gmail.com>
Date: Wed, 5 Jun 2013 14:55:01 +1000
Subject: [PATCH] Stub wsbh/wsbw for x86.

---
 Core/MIPS/x86/CompALU.cpp | 29 +++++++++++++++++++++++++++++
 Core/MIPS/x86/Jit.h       |  1 +
 2 files changed, 30 insertions(+)

diff --git a/Core/MIPS/x86/CompALU.cpp b/Core/MIPS/x86/CompALU.cpp
index f14343240f..539a181abc 100644
--- a/Core/MIPS/x86/CompALU.cpp
+++ b/Core/MIPS/x86/CompALU.cpp
@@ -711,6 +711,35 @@ namespace MIPSComp
 		}
 	}
 
+	void Jit::Comp_Allegrex2(u32 op)
+	{
+		CONDITIONAL_DISABLE
+		int rt = _RT;
+		int rd = _RD;
+		// Don't change $zr.
+		if (rd == 0)
+			return;
+
+		DISABLE;
+		switch (op & 0x3ff)
+		{
+		case 0xA0: //wsbh
+			gpr.Lock(rd, rt);
+			gpr.BindToRegister(rd, rd == rt, true);
+			// Stub
+			gpr.UnlockAll();
+			break;
+		case 0xE0: //wsbw
+			gpr.Lock(rd, rt);
+			gpr.BindToRegister(rd, rd == rt, true);
+			// Stub
+			gpr.UnlockAll();
+			break;
+		default:
+			Comp_Generic(op);
+			break;
+		}
+	}
 
 	void Jit::Comp_MulDivType(u32 op)
 	{
diff --git a/Core/MIPS/x86/Jit.h b/Core/MIPS/x86/Jit.h
index 705faedddb..0182705ee1 100644
--- a/Core/MIPS/x86/Jit.h
+++ b/Core/MIPS/x86/Jit.h
@@ -185,6 +185,7 @@ public:
 	void Comp_RType3(u32 op);
 	void Comp_ShiftType(u32 op);
 	void Comp_Allegrex(u32 op);
+	void Comp_Allegrex2(u32 op);
 	void Comp_VBranch(u32 op);
 	void Comp_MulDivType(u32 op);
 	void Comp_Special3(u32 op);