From 9bf8bfbed4e69c9bb3f62936b09e5bc4f381df39 Mon Sep 17 00:00:00 2001
From: Henrik Rydgard <hrydgard@gmail.com>
Date: Wed, 31 Jul 2013 11:22:04 +0200
Subject: [PATCH] armjit clamp: Clamp negative 0 to positive 0.

---
 Core/MIPS/ARM/ArmCompVFPU.cpp    | 2 +-
 Core/MIPS/ARM/ArmRegCacheFPU.cpp | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/Core/MIPS/ARM/ArmCompVFPU.cpp b/Core/MIPS/ARM/ArmCompVFPU.cpp
index 5a3d6493e5..ba75bfb396 100644
--- a/Core/MIPS/ARM/ArmCompVFPU.cpp
+++ b/Core/MIPS/ARM/ArmCompVFPU.cpp
@@ -185,7 +185,7 @@ namespace MIPSComp
 				MOVI2F(S0, 0.0f, R0);
 				MOVI2F(S1, 1.0f, R0);
 				VCMP(fpr.V(vregs[i]), S0);
-				SetCC(CC_LT);
+				SetCC(CC_LE);
 				VMOV(fpr.V(vregs[i]), S0);
 				SetCC(CC_AL);
 				VCMP(fpr.V(vregs[i]), S1);
diff --git a/Core/MIPS/ARM/ArmRegCacheFPU.cpp b/Core/MIPS/ARM/ArmRegCacheFPU.cpp
index 772eeb4f28..c4e9f3fd14 100644
--- a/Core/MIPS/ARM/ArmRegCacheFPU.cpp
+++ b/Core/MIPS/ARM/ArmRegCacheFPU.cpp
@@ -370,7 +370,7 @@ void ArmRegCacheFPU::ReleaseSpillLocksAndDiscardTemps() {
 		DiscardR(i);
 }
 
-ARMReg ArmRegCacheFPU::R(int mipsReg) {
+ARMReg ArmRegCacheFPU::R(int mi psReg) {
 	if (mr[mipsReg].loc == ML_ARMREG) {
 		return (ARMReg)(mr[mipsReg].reg + S0);
 	} else {