From 9a8ac1fe086dde4a6d8f3cdf0f2f4c10caedf30f Mon Sep 17 00:00:00 2001
From: "Unknown W. Brackets" <checkins@unknownbrackets.org>
Date: Sat, 29 Jul 2023 18:49:45 -0700
Subject: [PATCH] x86jit: Implement ll/sc.

The point here is that breakpoints now work for ll and sc.
---
 Core/MIPS/x86/CompLoadStore.cpp | 33 ++++++++++++++++++++++++++++++++-
 1 file changed, 32 insertions(+), 1 deletion(-)

diff --git a/Core/MIPS/x86/CompLoadStore.cpp b/Core/MIPS/x86/CompLoadStore.cpp
index 9ef4b0b206..603e3e367a 100644
--- a/Core/MIPS/x86/CompLoadStore.cpp
+++ b/Core/MIPS/x86/CompLoadStore.cpp
@@ -44,6 +44,7 @@
 // #define CONDITIONAL_DISABLE(flag) { Comp_Generic(op); return; }
 #define CONDITIONAL_DISABLE(flag) if (jo.Disabled(JitDisable::flag)) { Comp_Generic(op); return; }
 #define DISABLE { Comp_Generic(op); return; }
+#define INVALIDOP { Comp_Generic(op); return; }
 
 namespace MIPSComp {
 	using namespace Gen;
@@ -408,7 +409,37 @@ namespace MIPSComp {
 	void Jit::Comp_StoreSync(MIPSOpcode op) {
 		CONDITIONAL_DISABLE(LSU);
 
-		DISABLE;
+		int offset = _IMM16;
+		MIPSGPReg rt = _RT;
+		MIPSGPReg rs = _RS;
+		// Note: still does something even if loading to zero.
+
+		CheckMemoryBreakpoint(0, rs, offset);
+
+		FixupBranch skipStore;
+		FixupBranch finish;
+		switch (op >> 26) {
+		case 48: // ll
+			CompITypeMemRead(op, 32, &XEmitter::MOVZX, safeMemFuncs.readU32);
+			MOV(8, MDisp(X64JitConstants::CTXREG, -128 + offsetof(MIPSState, llBit)), Imm8(1));
+			break;
+
+		case 56: // sc
+			CMP(8, MDisp(X64JitConstants::CTXREG, -128 + offsetof(MIPSState, llBit)), Imm8(1));
+			skipStore = J_CC(CC_NE);
+
+			CompITypeMemWrite(op, 32, safeMemFuncs.writeU32);
+			MOV(32, gpr.R(rt), Imm32(1));
+			finish = J();
+
+			SetJumpTarget(skipStore);
+			MOV(32, gpr.R(rt), Imm32(0));
+			SetJumpTarget(finish);
+			break;
+
+		default:
+			INVALIDOP;
+		}
 	}
 
 	void Jit::Comp_Cache(MIPSOpcode op) {