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revert some accidenal commits

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This commit is contained in:
greenbagels 2014-06-29 16:49:31 -04:00
parent c4ced7a835
commit 9568dffee6
17 changed files with 37 additions and 89 deletions
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8
Core/Debugger/Breakpoints.cpp
View file

@ -83,7 +83,7 @@ void MemCheck::JitCleanup()
// Here's the tricky part: would this have changed memory?
// Note that it did not actually get written.
bool changed = MIPSAnalyst::OpWouldChangeMemory(lastPC, lastAddr, lastSize);
bool changed = MIPSAnalyst::OpWouldChangeMemory(lastPC, lastAddr);
if (changed)
{
++numHits;
@ -407,15 +407,15 @@ void CBreakPoints::Update(u32 addr)
if (Core_IsStepping() == false)
{
Core_EnableStepping(true);
Core_WaitInactive(200);
Core_WaitInactive();
resume = true;
}
// In case this is a delay slot, clear the previous instruction too.
if (addr != 0)
MIPSComp::jit->InvalidateCacheAt(addr - 4, 8);
MIPSComp::jit->ClearCacheAt(addr - 4, 8);
else
MIPSComp::jit->InvalidateCache();
MIPSComp::jit->ClearCache();
if (resume)
Core_EnableStepping(false);

2
Core/HLE/HLE.cpp
View file

@ -538,7 +538,7 @@ void CallSyscall(MIPSOpcode op)
CallSyscallWithoutFlags(info);
}
else
ERROR_LOG_REPORT(HLE, "Unimplemented HLE function %s", info->name ? info->name : "(\?\?\?)");
ERROR_LOG_REPORT(HLE, "Unimplemented HLE function %s", info->name ? info->name : "(???)");
if (g_Config.bShowDebugStats)
{

7
Core/HLE/sceKernel.cpp
View file

@ -364,8 +364,11 @@ int sceKernelDcacheInvalidateRange(u32 addr, int size)
}
int sceKernelIcacheInvalidateRange(u32 addr, int size) {
DEBUG_LOG(CPU, "sceKernelIcacheInvalidateRange(%08x, %i)", addr, size);
currentMIPS->InvalidateICache(addr, size);
DEBUG_LOG(CPU,"sceKernelIcacheInvalidateRange(%08x, %i)", addr, size);
// TODO: Make the JIT hash and compare the touched blocks.
if(MIPSComp::jit){
MIPSComp::jit->ClearCacheAt(addr, size);
}
return 0;
}

7
Core/MIPS/ARM/ArmJit.cpp
View file

@ -146,12 +146,7 @@ void Jit::ClearCache()
GenerateFixedCode();
}
void Jit::InvalidateCache()
{
blocks.Clear();
}
void Jit::InvalidateCacheAt(u32 em_address, int length)
void Jit::ClearCacheAt(u32 em_address, int length)
{
blocks.InvalidateICache(em_address, length);
}

3
Core/MIPS/ARM/ArmJit.h
View file

@ -178,8 +178,7 @@ public:
JitBlockCache *GetBlockCache() { return &blocks; }
void ClearCache();
void InvalidateCache();
void InvalidateCacheAt(u32 em_address, int length = 4);
void ClearCacheAt(u32 em_address, int length = 4);
void EatPrefix() { js.EatPrefix(); }

2
Core/MIPS/MIPS.cpp
View file

@ -328,5 +328,5 @@ u32 MIPSState::ReadFCR(int reg) {
void MIPSState::InvalidateICache(u32 address, int length) {
// Only really applies to jit.
if (MIPSComp::jit)
MIPSComp::jit->InvalidateCacheAt(address, length);
MIPSComp::jit->ClearCacheAt(address, length);
}

61
Core/MIPS/MIPSAnalyst.cpp
View file

@ -495,68 +495,29 @@ namespace MIPSAnalyst {
return (op & MIPSTABLE_IMM_MASK) == 0xB8000000;
}
static bool IsSWC1Instr(MIPSOpcode op) {
return (op & MIPSTABLE_IMM_MASK) == 0xE4000000;
}
static bool IsSVSInstr(MIPSOpcode op) {
return (op & MIPSTABLE_IMM_MASK) == 0xE8000000;
}
static bool IsSVQInstr(MIPSOpcode op) {
return (op & MIPSTABLE_IMM_MASK) == 0xF8000000;
}
bool OpWouldChangeMemory(u32 pc, u32 addr, u32 size) {
const auto op = Memory::Read_Instruction(pc);
// TODO: Trap sc/ll, svl.q, svr.q?
bool OpWouldChangeMemory(u32 pc, u32 addr) {
auto op = Memory::Read_Instruction(pc);
int gprMask = 0;
// TODO: swl/swr are annoying, not handled yet.
if (IsSWInstr(op))
gprMask = 0xFFFFFFFF;
if (IsSHInstr(op))
gprMask = 0x0000FFFF;
if (IsSBInstr(op))
gprMask = 0x000000FF;
if (IsSWLInstr(op)) {
const u32 shift = (addr & 3) * 8;
gprMask = 0xFFFFFFFF >> (24 - shift);
}
if (IsSWRInstr(op)) {
const u32 shift = (addr & 3) * 8;
gprMask = 0xFFFFFFFF << shift;
}
u32 writeVal = 0xFFFFFFFF;
u32 prevVal = 0x00000000;
if (gprMask != 0)
{
MIPSGPReg rt = MIPS_GET_RT(op);
writeVal = currentMIPS->r[rt] & gprMask;
prevVal = Memory::Read_U32(addr) & gprMask;
MIPSGPReg reg = MIPS_GET_RT(op);
u32 writeVal = currentMIPS->r[reg] & gprMask;
u32 prevVal = Memory::Read_U32(addr) & gprMask;
// TODO: Technically, the break might be for 1 byte in the middle of a sw.
return writeVal != prevVal;
}
if (IsSWC1Instr(op)) {
int ft = MIPS_GET_FT(op);
writeVal = currentMIPS->fi[ft];
prevVal = Memory::Read_U32(addr);
}
if (IsSVSInstr(op)) {
int vt = ((op >> 16) & 0x1f) | ((op & 3) << 5);
writeVal = currentMIPS->vi[voffset[vt]];
prevVal = Memory::Read_U32(addr);
}
if (IsSVQInstr(op)) {
int vt = (((op >> 16) & 0x1f)) | ((op & 1) << 5);
float rd[4];
ReadVector(rd, V_Quad, vt);
return memcmp(rd, Memory::GetPointer(addr), sizeof(float) * 4) != 0;
}
// TODO: Technically, the break might be for 1 byte in the middle of a sw.
return writeVal != prevVal;
// TODO: Not handled yet.
return true;
}
AnalysisResults Analyze(u32 address) {

2
Core/MIPS/MIPSAnalyst.h
View file

@ -127,7 +127,7 @@ namespace MIPSAnalyst
bool IsDelaySlotNiceFPU(MIPSOpcode branchOp, MIPSOpcode op);
bool IsSyscall(MIPSOpcode op);
bool OpWouldChangeMemory(u32 pc, u32 addr, u32 size);
bool OpWouldChangeMemory(u32 pc, u32 addr);
void Shutdown();

2
Core/MIPS/MIPSInt.cpp
View file

@ -133,7 +133,7 @@ namespace MIPSInt
case 8:
// Invalidate the instruction cache at this address
if (MIPSComp::jit) {
MIPSComp::jit->InvalidateCacheAt(addr, 0x40);
MIPSComp::jit->ClearCacheAt(addr, 0x40);
}
break;

6
Core/MIPS/PPC/PpcJit.cpp
View file

@ -217,11 +217,7 @@ void Jit::ClearCache() {
GenerateFixedCode();
}
void Jit::InvalidateCache() {
blocks.Clear();
}
void Jit::InvalidateCacheAt(u32 em_address, int length) {
void Jit::ClearCacheAt(u32 em_address, int length) {
blocks.InvalidateICache(em_address, length);
}

3
Core/MIPS/PPC/PpcJit.h
View file

@ -286,8 +286,7 @@ namespace MIPSComp
void WriteSyscallExit();
void ClearCache();
void InvalidateCache();
void InvalidateCacheAt(u32 em_address, int length = 4);
void ClearCacheAt(u32 em_address, int length = 4);
void RunLoopUntil(u64 globalticks);
void GenerateFixedCode();

7
Core/MIPS/x86/Jit.cpp
View file

@ -218,12 +218,7 @@ void Jit::ClearCache()
ClearCodeSpace();
}
void Jit::InvalidateCache()
{
blocks.Clear();
}
void Jit::InvalidateCacheAt(u32 em_address, int length)
void Jit::ClearCacheAt(u32 em_address, int length)
{
blocks.InvalidateICache(em_address, length);
}

3
Core/MIPS/x86/Jit.h
View file

@ -168,8 +168,7 @@ public:
AsmRoutineManager &Asm() { return asm_; }
void ClearCache();
void InvalidateCache();
void InvalidateCacheAt(u32 em_address, int length = 4);
void ClearCacheAt(u32 em_address, int length = 4);
private:
void GetStateAndFlushAll(RegCacheState &state);

2
GPU/GLES/Framebuffer.cpp
View file

@ -2094,7 +2094,7 @@ bool FramebufferManager::NotifyFramebufferCopy(u32 src, u32 dst, int size, bool
const u32 vfb_size = FramebufferByteSize(vfb);
const u32 vfb_bpp = vfb->format == GE_FORMAT_8888 ? 4 : 2;
const u32 vfb_byteStride = vfb->fb_stride * vfb_bpp;
const int vfb_byteWidth = vfb->width * vfb_bpp;
const u32 vfb_byteWidth = vfb->width * vfb_bpp;
if (dst >= vfb_address && (dst + size <= vfb_address + vfb_size || dst == vfb_address)) {
const u32 offset = dst - vfb_address;

7
GPU/GLES/StencilBuffer.cpp
View file

@ -50,6 +50,10 @@ static const char *stencil_vs =
" gl_Position = a_position;\n"
"}\n";
static bool MaskedEqual(u32 addr1, u32 addr2) {
return (addr1 & 0x03FFFFFF) == (addr2 & 0x03FFFFFF);
}
bool FramebufferManager::NotifyStencilUpload(u32 addr, int size) {
if (!MayIntersectFramebuffer(addr)) {
return false;
@ -107,9 +111,6 @@ bool FramebufferManager::NotifyStencilUpload(u32 addr, int size) {
case GE_FORMAT_8888:
values = 256;
break;
case GE_FORMAT_INVALID:
// Impossible.
break;
}
if (dstBuffer->fbo) {

2
GPU/GLES/TextureCache.cpp
View file

@ -1083,7 +1083,7 @@ void TextureCache::SetTextureFramebuffer(TexCacheEntry *entry, VirtualFramebuffe
gstate_c.flipTexture = true;
gstate_c.curTextureXOffset = fbTexInfo_[entry->addr].xOffset;
gstate_c.curTextureYOffset = fbTexInfo_[entry->addr].yOffset;
gstate_c.needShaderTexClamp = gstate_c.curTextureWidth != (u32)gstate.getTextureWidth(0) || gstate_c.curTextureHeight != (u32)gstate.getTextureHeight(0);
gstate_c.needShaderTexClamp = gstate_c.curTextureWidth != gstate.getTextureWidth(0) || gstate_c.curTextureHeight != gstate.getTextureHeight(0);
if (gstate_c.curTextureXOffset != 0 || gstate_c.curTextureYOffset != 0) {
gstate_c.needShaderTexClamp = true;
}

2
Windows/Debugger/CtrlDisAsmView.cpp
View file

@ -298,7 +298,7 @@ void CtrlDisAsmView::assembleOpcode(u32 address, std::string defaultText)
Memory::Write_U32(encoded, address);
// In case this is a delay slot or combined instruction, clear cache above it too.
if (MIPSComp::jit)
MIPSComp::jit->InvalidateCacheAt(address - 4, 8);
MIPSComp::jit->ClearCacheAt(address - 4, 8);
scanFunctions();
if (address == curAddress)