From 91966824bbb8dc54783d9064ffe8260d81e86dc0 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Henrik=20Rydg=C3=A5rd?= <hrydgard@gmail.com>
Date: Sat, 11 Oct 2014 15:57:08 +0200
Subject: [PATCH] minor cleanup: No point in having special functions for
 ReadFCR/WriteFCR, they're smaller than many other ops..

---
 Core/MIPS/MIPS.cpp    | 25 ------------------------
 Core/MIPS/MIPS.h      |  3 ---
 Core/MIPS/MIPSInt.cpp | 45 +++++++++++++++++++++++++++++++++++--------
 3 files changed, 37 insertions(+), 36 deletions(-)

diff --git a/Core/MIPS/MIPS.cpp b/Core/MIPS/MIPS.cpp
index 9e8ad38d5b..2277169f80 100644
--- a/Core/MIPS/MIPS.cpp
+++ b/Core/MIPS/MIPS.cpp
@@ -305,31 +305,6 @@ int MIPSState::RunLoopUntil(u64 globalTicks) {
 	return 1;
 }
 
-void MIPSState::WriteFCR(int reg, int value) {
-	if (reg == 31) {
-		fcr31 = value & 0x0181FFFF;
-		fpcond = (value >> 23) & 1;
-	} else {
-		WARN_LOG_REPORT(CPU, "WriteFCR: Unexpected reg %d (value %08x)", reg, value);
-		// MessageBox(0, "Invalid FCR","...",0);
-	}
-	DEBUG_LOG(CPU, "FCR%i written to, value %08x", reg, value);
-}
-
-u32 MIPSState::ReadFCR(int reg) {
-	DEBUG_LOG(CPU,"FCR%i read",reg);
-	if (reg == 31) {
-		fcr31 = (fcr31 & ~(1<<23)) | ((fpcond & 1)<<23);
-		return fcr31;
-	} else if (reg == 0) {
-		return FCR0_VALUE;
-	} else {
-		WARN_LOG_REPORT(CPU, "ReadFCR: Unexpected reg %d", reg);
-		// MessageBox(0, "Invalid FCR","...",0);
-	}
-	return 0;
-}
-
 void MIPSState::InvalidateICache(u32 address, int length) {
 	// Only really applies to jit.
 	if (MIPSComp::jit)
diff --git a/Core/MIPS/MIPS.h b/Core/MIPS/MIPS.h
index c9e7c35cc8..4a69dcd345 100644
--- a/Core/MIPS/MIPS.h
+++ b/Core/MIPS/MIPS.h
@@ -178,9 +178,6 @@ public:
 
 	static const u32 FCR0_VALUE = 0x00003351;
 
-	void WriteFCR(int reg, int value);
-	u32 ReadFCR(int reg);
-
 	u8 VfpuWriteMask() const {
 		return (vfpuCtrl[VFPU_CTRL_DPREFIX] >> 8) & 0xF;
 	}
diff --git a/Core/MIPS/MIPSInt.cpp b/Core/MIPS/MIPSInt.cpp
index 45d88f5f43..330f29a054 100644
--- a/Core/MIPS/MIPSInt.cpp
+++ b/Core/MIPS/MIPSInt.cpp
@@ -527,12 +527,41 @@ namespace MIPSInt
 		int fs = _FS;
 		int rt = _RT;
 
-		switch((op>>21)&0x1f) 
-		{
-		case 0: if (rt != 0) R(rt) = FI(fs); break; //mfc1
-		case 2: if (rt != 0) R(rt) = currentMIPS->ReadFCR(fs); break; //cfc1
-		case 4: FI(fs) = R(rt);	break; //mtc1
-		case 6: currentMIPS->WriteFCR(fs, R(rt)); break; //ctc1
+		switch ((op>>21)&0x1f) {
+		case 0: //mfc1
+			if (rt != 0)
+				R(rt) = FI(fs);
+			break;
+
+		case 2: //cfc1
+			if (rt != 0) {
+				if (fs == 31) {
+					currentMIPS->fcr31 = (currentMIPS->fcr31 & ~(1<<23)) | ((currentMIPS->fpcond & 1)<<23);
+					R(rt) = currentMIPS->fcr31;
+				} else if (fs == 0) {
+					R(rt) = MIPSState::FCR0_VALUE;
+				} else {
+					WARN_LOG_REPORT(CPU, "ReadFCR: Unexpected reg %d", fs);
+				}
+				break;
+			}
+
+		case 4: //mtc1
+			FI(fs) = R(rt);
+			break;
+
+		case 6: //ctc1
+			{
+				u32 value = R(rt);
+				if (fs == 31) {
+					currentMIPS->fcr31 = value & 0x0181FFFF;
+					currentMIPS->fpcond = (value >> 23) & 1;
+				} else {
+					WARN_LOG_REPORT(CPU, "WriteFCR: Unexpected reg %d (value %08x)", fs, value);
+				}
+				DEBUG_LOG(CPU, "FCR%i written to, value %08x", fs, value);
+				break;
+			}
 		
 		default:
 			_dbg_assert_msg_(CPU,0,"Trying to interpret instruction that can't be interpreted");
@@ -818,14 +847,14 @@ namespace MIPSInt
 		static int reported = 0;
 		switch (op & 0x3F)
 		{
-		case 36:
+		case 36:  // mfic
 			if (!reported) {
 				Reporting::ReportMessage("MFIC instruction hit (%08x) at %08x", op, currentMIPS->pc);
 				WARN_LOG(CPU,"MFIC Disable/Enable Interrupt CPU instruction");
 				reported = 1;
 			}
 			break;
-		case 38:
+		case 38:  // mtic
 			if (!reported) {
 				Reporting::ReportMessage("MTIC instruction hit (%08x) at %08x", op, currentMIPS->pc);
 				WARN_LOG(CPU,"MTIC Disable/Enable Interrupt CPU instruction");