From 8ea7f990722809fc43324ea81360558aade120d4 Mon Sep 17 00:00:00 2001 From: "Unknown W. Brackets" Date: Sat, 4 Jul 2015 07:08:27 -0700 Subject: [PATCH] arm64: Fix imm wasting when STP doesn't work out. --- Core/MIPS/ARM64/Arm64RegCache.cpp | 11 +++++++++-- unittest/TestArm64Emitter.cpp | 4 ++-- 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/Core/MIPS/ARM64/Arm64RegCache.cpp b/Core/MIPS/ARM64/Arm64RegCache.cpp index 12b67ec328..03a0b32348 100644 --- a/Core/MIPS/ARM64/Arm64RegCache.cpp +++ b/Core/MIPS/ARM64/Arm64RegCache.cpp @@ -448,15 +448,22 @@ void Arm64RegCache::FlushAll() { // If either one doesn't have a reg yet, try flushing imms to scratch regs. if (areg1 == INVALID_REG && IsImm(mreg1)) { - SetRegImm(SCRATCH1, GetImm(mreg1)); areg1 = SCRATCH1; } if (areg2 == INVALID_REG && IsImm(mreg2)) { - SetRegImm(SCRATCH2, GetImm(mreg2)); areg2 = SCRATCH2; } if (areg1 != INVALID_REG && areg2 != INVALID_REG) { + // Actually put the imms in place now that we know we can do the STP. + // We didn't do it before in case the other wouldn't work. + if (areg1 == SCRATCH1) { + SetRegImm(areg1, GetImm(mreg1)); + } + if (areg2 == SCRATCH2) { + SetRegImm(areg2, GetImm(mreg2)); + } + // We can use a paired store, awesome. emit_->STP(INDEX_SIGNED, areg1, areg2, CTXREG, GetMipsRegOffset(mreg1)); diff --git a/unittest/TestArm64Emitter.cpp b/unittest/TestArm64Emitter.cpp index 7e2e8e6525..8129863579 100644 --- a/unittest/TestArm64Emitter.cpp +++ b/unittest/TestArm64Emitter.cpp @@ -48,9 +48,9 @@ bool TestArm64Emitter() { fp.UCVTF(32, D3, D7, 15); RET(CheckLast(emitter, "2f31e4e3 ucvtf d3.s, d7.s, #15")); - fp.LDP(INDEX_SIGNED, Q3, Q7, X3, 32); + fp.LDP(128, INDEX_SIGNED, Q3, Q7, X3, 32); RET(CheckLast(emitter, "ad411c63 ldp q3, q7, [x3, #32]")); - fp.STP(INDEX_SIGNED, Q3, Q7, X3, 32); + fp.STP(128, INDEX_SIGNED, Q3, Q7, X3, 32); RET(CheckLast(emitter, "ad011c63 stp q3, q7, [x3, #32]")); fp.DUP(32, Q1, Q30, 3);