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https://github.com/hrydgard/ppsspp.git
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Merge pull request #2647 from unknownbrackets/jit-minor
Fix x64 jit bugs (memchecks and lwl/lwr/swl/swr)
This commit is contained in:
Henrik Rydgård
commit
8988d697e3
6 changed files with 133 additions and 61 deletions
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@ -559,6 +559,7 @@ void XEmitter::ABI_PushAllCalleeSavedRegsAndAdjustStack() {
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PUSH(R14);
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PUSH(R15);
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PUSH(R15); //just to align stack. duped push/pop doesn't hurt.
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// TODO: XMM?
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}
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void XEmitter::ABI_PopAllCalleeSavedRegsAndAdjustStack() {
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@ -57,6 +57,14 @@ public:
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Shutdown();
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}
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void *ProtectFunction(void *function, int num_params);
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const u8 *GetSaveRegsFunction() const {
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return save_regs;
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}
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const u8 *GetLoadRegsFunction() const {
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return load_regs;
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}
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private:
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void Init();
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void Shutdown();
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@ -104,25 +104,28 @@ namespace MIPSComp
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void Jit::CompITypeMemUnpairedLR(u32 op, bool isStore)
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{
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// TODO: ECX getting overwritten? Why?
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DISABLE;
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CONDITIONAL_DISABLE;
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int o = op>>26;
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int offset = (signed short)(op&0xFFFF);
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int rt = _RT;
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int rs = _RS;
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X64Reg shiftReg = ECX;
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gpr.FlushLockX(ECX, EDX);
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#ifdef _M_X64
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// On x64, we need ECX for CL, but it's also the first arg and gets lost. Annoying.
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gpr.FlushLockX(R9);
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shiftReg = R9;
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#endif
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gpr.Lock(rt);
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gpr.BindToRegister(rt, true, !isStore);
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// Grab the offset from alignment for shifting (<< 3 for bytes -> bits.)
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MOV(32, R(ECX), gpr.R(rs));
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ADD(32, R(ECX), Imm32(offset));
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AND(32, R(ECX), Imm32(3));
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SHL(32, R(ECX), Imm8(3));
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MOV(32, R(shiftReg), gpr.R(rs));
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ADD(32, R(shiftReg), Imm32(offset));
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AND(32, R(shiftReg), Imm32(3));
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SHL(32, R(shiftReg), Imm8(3));
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{
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JitSafeMem safe(this, rs, offset, ~3);
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@ -133,10 +136,10 @@ namespace MIPSComp
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if (!src.IsSimpleReg(EAX))
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MOV(32, R(EAX), src);
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CompITypeMemUnpairedLRInner(op);
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CompITypeMemUnpairedLRInner(op, shiftReg);
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}
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if (safe.PrepareSlowRead((void *) &Memory::Read_U32))
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CompITypeMemUnpairedLRInner(op);
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CompITypeMemUnpairedLRInner(op, shiftReg);
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safe.Finish();
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}
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@ -156,37 +159,69 @@ namespace MIPSComp
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gpr.UnlockAllX();
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}
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void Jit::CompITypeMemUnpairedLRInner(u32 op)
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void Jit::CompITypeMemUnpairedLRInner(u32 op, X64Reg shiftReg)
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{
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CONDITIONAL_DISABLE;
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int o = op>>26;
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int rt = _RT;
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// Make sure we have the shift for the target in ECX.
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if (shiftReg != ECX)
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MOV(32, R(ECX), R(shiftReg));
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// Now use that shift (left on target, right on source.)
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switch (o)
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{
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case 34: //lwl
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// First clear the target bits.
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MOV(32, R(EDX), Imm32(0x00ffffff));
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SHR(32, R(EDX), R(CL));
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AND(32, gpr.R(rt), R(EDX));
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break;
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// Adjust the shift to the bits we want.
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case 38: //lwr
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SHR(32, R(EAX), R(CL));
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break;
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case 42: //swl
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MOV(32, R(EDX), Imm32(0xffffff00));
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SHL(32, R(EDX), R(CL));
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AND(32, R(EAX), R(EDX));
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break;
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case 46: //swr
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MOV(32, R(EDX), gpr.R(rt));
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SHL(32, R(EDX), R(CL));
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// EDX is already the target value to write, but may be overwritten below. Save it.
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PUSH(EDX);
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break;
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default:
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_dbg_assert_msg_(JIT, 0, "Unsupported left/right load/store instruction.");
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}
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// Flip ECX around from 3 bytes / 24 bits.
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if (shiftReg == ECX)
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{
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MOV(32, R(EDX), Imm32(24));
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SUB(32, R(EDX), R(ECX));
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MOV(32, R(ECX), R(EDX));
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}
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else
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{
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MOV(32, R(ECX), Imm32(24));
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SUB(32, R(ECX), R(shiftReg));
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}
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// Use the flipped shift (left on source, right on target) and write target.
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switch (o)
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{
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case 34: //lwl
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SHL(32, R(EAX), R(CL));
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OR(32, gpr.R(rt), R(EAX));
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break;
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case 38: //lwr
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// Adjust the shift to the bits we want.
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SHR(32, R(EAX), R(CL));
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// Clear the target bits we're replacing.
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MOV(32, R(EDX), Imm32(24));
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SUB(32, R(EDX), R(ECX));
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MOV(32, R(ECX), R(EDX));
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MOV(32, R(EDX), Imm32(0xffffff00));
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SHL(32, R(EDX), R(CL));
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AND(32, gpr.R(rt), R(EDX));
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@ -195,15 +230,6 @@ namespace MIPSComp
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break;
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case 42: //swl
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// First clear the target memory bits.
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MOV(32, R(EDX), Imm32(0xffffff00));
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SHL(32, R(EDX), R(CL));
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AND(32, R(EAX), R(EDX));
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// Flip the shift, and adjust the shift in a temporary.
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MOV(32, R(EDX), Imm32(24));
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SUB(32, R(EDX), R(ECX));
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MOV(32, R(ECX), R(EDX));
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MOV(32, R(EDX), gpr.R(rt));
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SHR(32, R(EDX), R(CL));
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@ -211,19 +237,11 @@ namespace MIPSComp
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break;
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case 46: //swr
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// Adjust the shift to the bits we want.
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MOV(32, R(EDX), gpr.R(rt));
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SHL(32, R(EDX), R(CL));
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PUSH(EDX);
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// Clear the target bits we're replacing.
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MOV(32, R(EDX), Imm32(24));
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SUB(32, R(EDX), R(ECX));
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MOV(32, R(ECX), R(EDX));
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MOV(32, R(EDX), Imm32(0x00ffffff));
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SHR(32, R(EDX), R(CL));
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AND(32, R(EAX), R(EDX));
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// This is the target value we saved earlier.
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POP(EDX);
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OR(32, R(EDX), R(EAX));
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break;
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@ -292,14 +292,17 @@ const u8 *Jit::DoJit(u32 em_address, JitBlock *b)
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{
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// TODO: Save/restore?
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FlushAll();
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CMP(32, M((void*)&coreState), Imm32(0));
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FixupBranch skipCheck = J_CC(CC_E);
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CMP(32, M((void*)&coreState), Imm32(CORE_RUNNING));
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FixupBranch skipCheck1 = J_CC(CC_E);
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CMP(32, M((void*)&coreState), Imm32(CORE_NEXTFRAME));
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FixupBranch skipCheck2 = J_CC(CC_E);
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if (js.afterOp & JitState::AFTER_REWIND_PC_BAD_STATE)
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MOV(32, M(&mips_->pc), Imm32(js.compilerPC));
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else
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MOV(32, M(&mips_->pc), Imm32(js.compilerPC + 4));
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WriteSyscallExit();
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SetJumpTarget(skipCheck);
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SetJumpTarget(skipCheck1);
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SetJumpTarget(skipCheck2);
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js.afterOp = JitState::AFTER_NONE;
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}
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@ -355,11 +358,14 @@ void Jit::WriteExit(u32 destination, int exit_num)
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// If we need to verify coreState and rewind, we may not jump yet.
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if (js.afterOp & (JitState::AFTER_CORE_STATE | JitState::AFTER_REWIND_PC_BAD_STATE))
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{
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CMP(32, M((void*)&coreState), Imm32(0));
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FixupBranch skipCheck = J_CC(CC_E);
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CMP(32, M((void*)&coreState), Imm32(CORE_RUNNING));
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FixupBranch skipCheck1 = J_CC(CC_E);
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CMP(32, M((void*)&coreState), Imm32(CORE_NEXTFRAME));
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FixupBranch skipCheck2 = J_CC(CC_E);
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MOV(32, M(&mips_->pc), Imm32(js.compilerPC));
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WriteSyscallExit();
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SetJumpTarget(skipCheck);
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SetJumpTarget(skipCheck1);
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SetJumpTarget(skipCheck2);
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js.afterOp = JitState::AFTER_NONE;
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}
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@ -392,11 +398,14 @@ void Jit::WriteExitDestInEAX()
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// If we need to verify coreState and rewind, we may not jump yet.
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if (js.afterOp & (JitState::AFTER_CORE_STATE | JitState::AFTER_REWIND_PC_BAD_STATE))
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{
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CMP(32, M((void*)&coreState), Imm32(0));
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FixupBranch skipCheck = J_CC(CC_E);
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CMP(32, M((void*)&coreState), Imm32(CORE_RUNNING));
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FixupBranch skipCheck1 = J_CC(CC_E);
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CMP(32, M((void*)&coreState), Imm32(CORE_NEXTFRAME));
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FixupBranch skipCheck2 = J_CC(CC_E);
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MOV(32, M(&mips_->pc), Imm32(js.compilerPC));
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WriteSyscallExit();
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SetJumpTarget(skipCheck);
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SetJumpTarget(skipCheck1);
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SetJumpTarget(skipCheck2);
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js.afterOp = JitState::AFTER_NONE;
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}
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@ -418,13 +427,13 @@ void Jit::WriteExitDestInEAX()
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SetJumpTarget(tooLow);
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SetJumpTarget(tooHigh);
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ABI_CallFunctionA(thunks.ProtectFunction((void *) Memory::GetPointer, 1), R(EAX));
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CallProtectedFunction((void *) Memory::GetPointer, R(EAX));
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CMP(32, R(EAX), Imm32(0));
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FixupBranch skip = J_CC(CC_NE);
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// TODO: "Ignore" this so other threads can continue?
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if (g_Config.bIgnoreBadMemAccess)
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ABI_CallFunctionA(thunks.ProtectFunction((void *) Core_UpdateState, 1), Imm32(CORE_ERROR));
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CallProtectedFunction((void *) Core_UpdateState, Imm32(CORE_ERROR));
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SUB(32, M(¤tMIPS->downcount), Imm32(0));
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JMP(asm_.dispatcherCheckCoreState, true);
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@ -607,7 +616,6 @@ OpArg Jit::JitSafeMem::PrepareMemoryOpArg(ReadType type)
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jit_->SUB(32, R(xaddr_), Imm32(offset_));
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}
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#ifdef _M_IX86
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return MDisp(xaddr_, (u32) Memory::base + offset_);
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#else
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@ -657,7 +665,7 @@ void Jit::JitSafeMem::DoSlowWrite(void *safeFunc, const OpArg src, int suboffset
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jit_->AND(32, R(EAX), Imm32(alignMask_));
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}
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jit_->ABI_CallFunctionAA(jit_->thunks.ProtectFunction(safeFunc, 2), src, R(EAX));
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jit_->CallProtectedFunction(safeFunc, src, R(EAX));
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needsCheck_ = true;
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}
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@ -680,7 +688,7 @@ bool Jit::JitSafeMem::PrepareSlowRead(void *safeFunc)
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jit_->AND(32, R(EAX), Imm32(alignMask_));
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}
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jit_->ABI_CallFunctionA(jit_->thunks.ProtectFunction(safeFunc, 1), R(EAX));
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jit_->CallProtectedFunction(safeFunc, R(EAX));
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needsCheck_ = true;
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return true;
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}
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@ -710,7 +718,7 @@ void Jit::JitSafeMem::NextSlowRead(void *safeFunc, int suboffset)
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jit_->AND(32, R(EAX), Imm32(alignMask_));
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}
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jit_->ABI_CallFunctionA(jit_->thunks.ProtectFunction(safeFunc, 1), R(EAX));
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jit_->CallProtectedFunction(safeFunc, R(EAX));
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}
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bool Jit::JitSafeMem::ImmValid()
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@ -755,7 +763,7 @@ void Jit::JitSafeMem::MemCheckImm(ReadType type)
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return;
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jit_->MOV(32, M(&jit_->mips_->pc), Imm32(jit_->js.compilerPC));
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jit_->ABI_CallFunctionCCC(jit_->thunks.ProtectFunction((void *)&JitMemCheck, 3), iaddr_, size_, type == MEM_WRITE ? 1 : 0);
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jit_->CallProtectedFunction((void *)&JitMemCheck, iaddr_, size_, type == MEM_WRITE ? 1 : 0);
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jit_->CMP(32, M((void*)&coreState), Imm32(0));
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skipChecks_.push_back(jit_->J_CC(CC_NE, true));
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@ -790,11 +798,14 @@ void Jit::JitSafeMem::MemCheckAsm(ReadType type)
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skipNext = jit_->J_CC(CC_NE);
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}
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jit_->PUSH(xaddr_);
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// Keep the stack 16-byte aligned, just PUSH/POP 4 times.
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for (int i = 0; i < 4; ++i)
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jit_->PUSH(xaddr_);
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jit_->MOV(32, M(&jit_->mips_->pc), Imm32(jit_->js.compilerPC));
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jit_->ADD(32, R(xaddr_), Imm32(offset_));
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jit_->ABI_CallFunctionACC(jit_->thunks.ProtectFunction((void *)&JitMemCheck, 3), R(xaddr_), size_, type == MEM_WRITE ? 1 : 0);
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jit_->POP(xaddr_);
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jit_->CallProtectedFunction((void *)&JitMemCheck, R(xaddr_), size_, type == MEM_WRITE ? 1 : 0);
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for (int i = 0; i < 4; ++i)
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jit_->POP(xaddr_);
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jit_->SetJumpTarget(skipNext);
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if (it->end != 0)
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@ -809,6 +820,34 @@ void Jit::JitSafeMem::MemCheckAsm(ReadType type)
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}
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}
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void Jit::CallProtectedFunction(void *func, const OpArg &arg1)
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{
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// We don't regcache RCX, so the below is safe (and also faster, maybe branch prediction?)
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ABI_CallFunctionA(thunks.ProtectFunction(func, 1), arg1);
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}
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void Jit::CallProtectedFunction(void *func, const OpArg &arg1, const OpArg &arg2)
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{
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// We don't regcache RCX/RDX, so the below is safe (and also faster, maybe branch prediction?)
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ABI_CallFunctionAA(thunks.ProtectFunction(func, 2), arg1, arg2);
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}
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void Jit::CallProtectedFunction(void *func, const u32 arg1, const u32 arg2, const u32 arg3)
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{
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// On x64, we need to save R8, which is caller saved.
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ABI_CallFunction((void *)thunks.GetSaveRegsFunction());
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ABI_CallFunctionCCC(func, arg1, arg2, arg3);
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ABI_CallFunction((void *)thunks.GetLoadRegsFunction());
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}
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void Jit::CallProtectedFunction(void *func, const OpArg &arg1, const u32 arg2, const u32 arg3)
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{
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// On x64, we need to save R8, which is caller saved.
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ABI_CallFunction((void *)thunks.GetSaveRegsFunction());
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ABI_CallFunctionACC(func, arg1, arg2, arg3);
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ABI_CallFunction((void *)thunks.GetLoadRegsFunction());
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}
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void Jit::Comp_DoNothing(u32 op) { }
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} // namespace
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@ -275,11 +275,16 @@ private:
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void CompITypeMemRead(u32 op, u32 bits, void (XEmitter::*mov)(int, int, X64Reg, OpArg), void *safeFunc);
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void CompITypeMemWrite(u32 op, u32 bits, void *safeFunc);
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void CompITypeMemUnpairedLR(u32 op, bool isStore);
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void CompITypeMemUnpairedLRInner(u32 op);
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void CompITypeMemUnpairedLRInner(u32 op, X64Reg shiftReg);
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void CompFPTriArith(u32 op, void (XEmitter::*arith)(X64Reg reg, OpArg), bool orderMatters);
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void CompFPComp(int lhs, int rhs, u8 compare, bool allowNaN = false);
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void CallProtectedFunction(void *func, const OpArg &arg1);
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void CallProtectedFunction(void *func, const OpArg &arg1, const OpArg &arg2);
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void CallProtectedFunction(void *func, const u32 arg1, const u32 arg2, const u32 arg3);
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void CallProtectedFunction(void *func, const OpArg &arg1, const u32 arg2, const u32 arg3);
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JitBlockCache blocks;
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JitOptions jo;
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JitState js;
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@ -26,15 +26,16 @@ using namespace Gen;
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static const int allocationOrder[] =
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{
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// R12, when used as base register, for example in a LEA, can generate bad code! Need to look into this.
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// R12, when used as base register, for example in a LEA, can generate bad code! Need to look into this.
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// On x64, RCX and RDX are the first args. CallProtectedFunction() assumes they're not regcached.
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#ifdef _M_X64
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#ifdef _WIN32
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RSI, RDI, R13, R14, R8, R9, R10, R11, R12, //, RCX
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RSI, RDI, R13, R14, R8, R9, R10, R11, R12,
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#else
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RBP, R13, R14, R8, R9, R10, R11, R12, //, RCX
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RBP, R13, R14, R8, R9, R10, R11, R12,
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#endif
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#elif _M_IX86
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ESI, EDI, EBP, EDX, ECX, // Let's try to free up EBX as well.
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ESI, EDI, EBP, EDX, ECX, // Let's try to free up EBX as well.
|
||||
#endif
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue