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Cleanup some COP2/VFPU2 table flags.
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parent
3ae2b8dcc4
commit
7e92b17dd4
2 changed files with 34 additions and 35 deletions
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@ -230,6 +230,7 @@ namespace MIPSInt
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int imm = (signed short)(op&0xFFFF)<<2;
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u32 addr = PC + imm + 4;
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// x, y, z, w, any, all, (invalid), (invalid)
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int imm3 = (op>>18)&7;
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int val = (currentMIPS->vfpuCtrl[VFPU_CTRL_CC] >> imm3) & 1;
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@ -58,7 +58,7 @@ enum MipsEncoding
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ALLEGREX0,
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Emu,
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Rese,
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NumEncodings
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NumEncodings,
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};
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struct MIPSInstruction
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@ -251,17 +251,17 @@ const MIPSInstruction tableSpecial2[64] = // 011100 ..... ..... ..... ..... xxxx
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{
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INSTR("halt", &Jit::Comp_Generic, Dis_Generic, 0, 0),
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INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID,
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//8
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//8
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INVALID_X_8,
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INVALID_X_8,
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INVALID_X_8,
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//32
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//32
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INVALID, INVALID, INVALID, INVALID,
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INSTR("mfic", &Jit::Comp_Generic, Dis_Generic, 0, 0),
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INVALID,
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INSTR("mtic", &Jit::Comp_Generic, Dis_Generic, 0, 0),
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INVALID,
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//40
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//40
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INVALID_X_8,
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INVALID_X_8,
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INVALID_X_8,
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@ -281,22 +281,21 @@ const MIPSInstruction tableSpecial3[64] = // 011111 ..... ..... ..... ..... xxxx
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INVALID_X_8,
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//16
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INVALID_X_8,
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//24
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ENCODING(ALLEGREX0),
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INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID,
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//32
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ENCODING(ALLEGREX0),
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INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID,
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//40
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ENCODING(ALLEGREX0),
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INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID,
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INVALID_X_8,
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INVALID_X_8,
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//56
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INVALID, INVALID, INVALID,
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INSTR("rdhwr", &Jit::Comp_Generic, Dis_Generic, 0, 0),
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INVALID, INVALID, INVALID, INVALID,
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};
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const MIPSInstruction tableRegImm[32] = // 000001 ..... xxxxx ................
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{
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INSTR("bltz", &Jit::Comp_RelBranchRI, Dis_RelBranch, Int_RelBranchRI, IS_CONDBRANCH|IN_RS|DELAYSLOT|CONDTYPE_LTZ),
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@ -307,7 +306,7 @@ const MIPSInstruction tableRegImm[32] = // 000001 ..... xxxxx ................
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INVALID,
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INVALID,
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INVALID,
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//8
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INSTR("tgei", &Jit::Comp_Generic, Dis_Generic, 0, 0),
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INSTR("tgeiu", &Jit::Comp_Generic, Dis_Generic, 0, 0),
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INSTR("tlti", &Jit::Comp_Generic, Dis_Generic, 0, 0),
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@ -316,8 +315,8 @@ const MIPSInstruction tableRegImm[32] = // 000001 ..... xxxxx ................
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INVALID,
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INSTR("tnei", &Jit::Comp_Generic, Dis_Generic, 0, 0),
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INVALID,
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INSTR("bltzal", &Jit::Comp_RelBranchRI, Dis_RelBranch, Int_RelBranchRI, IS_CONDBRANCH|IN_RS|OUT_RA|DELAYSLOT|CONDTYPE_LTZ),
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//16
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INSTR("bltzal", &Jit::Comp_RelBranchRI, Dis_RelBranch, Int_RelBranchRI, IS_CONDBRANCH|IN_RS|OUT_RA|DELAYSLOT|CONDTYPE_LTZ),
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INSTR("bgezal", &Jit::Comp_RelBranchRI, Dis_RelBranch, Int_RelBranchRI, IS_CONDBRANCH|IN_RS|OUT_RA|DELAYSLOT|CONDTYPE_GEZ),
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INSTR("bltzall", &Jit::Comp_RelBranchRI, Dis_RelBranch, Int_RelBranchRI, IS_CONDBRANCH|IN_RS|OUT_RA|DELAYSLOT|LIKELY|CONDTYPE_LTZ), //L = likely
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INSTR("bgezall", &Jit::Comp_RelBranchRI, Dis_RelBranch, Int_RelBranchRI, IS_CONDBRANCH|IN_RS|OUT_RA|DELAYSLOT|LIKELY|CONDTYPE_GEZ),
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@ -325,22 +324,22 @@ const MIPSInstruction tableRegImm[32] = // 000001 ..... xxxxx ................
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INVALID,
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INVALID,
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INVALID,
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//24
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INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID,
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INSTR("synci", &Jit::Comp_Generic, Dis_Generic, 0, 0),
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};
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const MIPSInstruction tableCop2[32] =
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const MIPSInstruction tableCop2[32] = // 010010 xxxxx ..... ................
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{
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INSTR("mfc2", &Jit::Comp_Generic, Dis_Generic, 0, OUT_RT),
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INVALID,
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INSTR("cfc2", &Jit::Comp_Generic, Dis_Generic, 0, 0),
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INSTR("mfv", &Jit::Comp_Mftv, Dis_Mftv, Int_Mftv, IS_VFPU),
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INSTR("mfv", &Jit::Comp_Mftv, Dis_Mftv, Int_Mftv, IN_OTHER|OUT_RT|IS_VFPU),
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INSTR("mtc2", &Jit::Comp_Generic, Dis_Generic, 0, IN_RT),
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INVALID,
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INSTR("ctc2", &Jit::Comp_Generic, Dis_Generic, 0, 0),
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INSTR("mtv", &Jit::Comp_Mftv, Dis_Mftv, Int_Mftv, IS_VFPU),
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INSTR("mtv", &Jit::Comp_Mftv, Dis_Mftv, Int_Mftv, IN_RT|OUT_OTHER|IS_VFPU),
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//8
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ENCODING(Cop2BC2),
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INSTR("??", &Jit::Comp_Generic, Dis_Generic, 0, 0),
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INSTR("??", &Jit::Comp_Generic, Dis_Generic, 0, 0),
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@ -349,20 +348,20 @@ const MIPSInstruction tableCop2[32] =
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INSTR("??", &Jit::Comp_Generic, Dis_Generic, 0, 0),
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INSTR("??", &Jit::Comp_Generic, Dis_Generic, 0, 0),
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INSTR("??", &Jit::Comp_Generic, Dis_Generic, 0, 0),
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//16
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INVALID_X_8,
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INVALID_X_8,
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};
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const MIPSInstruction tableCop2BC2[4] =
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const MIPSInstruction tableCop2BC2[4] = // 010010 01000 ...xx ................
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{
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INSTR("bvf", &Jit::Comp_VBranch, Dis_VBranch, Int_VBranch, IS_CONDBRANCH|DELAYSLOT),
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INSTR("bvt", &Jit::Comp_VBranch, Dis_VBranch, Int_VBranch, IS_CONDBRANCH|DELAYSLOT),
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INSTR("bvfl", &Jit::Comp_VBranch, Dis_VBranch, Int_VBranch, IS_CONDBRANCH|DELAYSLOT|LIKELY),
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INSTR("bvtl", &Jit::Comp_VBranch, Dis_VBranch, Int_VBranch, IS_CONDBRANCH|DELAYSLOT|LIKELY),
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INSTR("bvf", &Jit::Comp_VBranch, Dis_VBranch, Int_VBranch, IS_CONDBRANCH|IN_OTHER|DELAYSLOT|IS_VFPU),
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INSTR("bvt", &Jit::Comp_VBranch, Dis_VBranch, Int_VBranch, IS_CONDBRANCH|IN_OTHER|DELAYSLOT|IS_VFPU),
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INSTR("bvfl", &Jit::Comp_VBranch, Dis_VBranch, Int_VBranch, IS_CONDBRANCH|IN_OTHER|DELAYSLOT|LIKELY|IS_VFPU),
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INSTR("bvtl", &Jit::Comp_VBranch, Dis_VBranch, Int_VBranch, IS_CONDBRANCH|IN_OTHER|DELAYSLOT|LIKELY|IS_VFPU),
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};
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const MIPSInstruction tableCop0[32] =
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const MIPSInstruction tableCop0[32] = // 010000 xxxxx ..... ................
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{
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INSTR("mfc0", &Jit::Comp_Generic, Dis_Generic, 0, OUT_RT),
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INVALID,
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@ -372,7 +371,7 @@ const MIPSInstruction tableCop0[32] =
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INVALID,
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INVALID,
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INVALID,
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//8
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INVALID,
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INVALID,
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INSTR("rdpgpr", &Jit::Comp_Generic, Dis_Generic, 0, 0),
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@ -382,13 +381,13 @@ const MIPSInstruction tableCop0[32] =
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INVALID,
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INSTR("wrpgpr", &Jit::Comp_Generic, Dis_Generic, 0, 0),
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INVALID,
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//16
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ENCODING(Cop0CO), ENCODING(Cop0CO), ENCODING(Cop0CO), ENCODING(Cop0CO), ENCODING(Cop0CO), ENCODING(Cop0CO), ENCODING(Cop0CO), ENCODING(Cop0CO),
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ENCODING(Cop0CO), ENCODING(Cop0CO), ENCODING(Cop0CO), ENCODING(Cop0CO), ENCODING(Cop0CO), ENCODING(Cop0CO), ENCODING(Cop0CO), ENCODING(Cop0CO),
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};
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// we won't encounter these since we only do user mode emulation
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const MIPSInstruction tableCop0CO[64] =
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const MIPSInstruction tableCop0CO[64] = // 010000 1.... ..... ..... ..... xxxxxx
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{
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INVALID,
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INSTR("tlbr", &Jit::Comp_Generic, Dis_Generic, 0, 0),
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@ -398,25 +397,24 @@ const MIPSInstruction tableCop0CO[64] =
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INVALID,
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INSTR("tlbwr", &Jit::Comp_Generic, Dis_Generic, 0, 0),
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INVALID,
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//8
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INSTR("tlbp", &Jit::Comp_Generic, Dis_Generic, 0, 0),
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INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID,
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INVALID_X_8,
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//24
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INSTR("eret", &Jit::Comp_Generic, Dis_Generic, 0, 0),
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INSTR("iack", &Jit::Comp_Generic, Dis_Generic, 0, 0),
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INVALID, INVALID, INVALID, INVALID, INVALID,
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INSTR("deret", &Jit::Comp_Generic, Dis_Generic, 0, 0),
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//32
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INSTR("wait", &Jit::Comp_Generic, Dis_Generic, 0, 0),
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INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID,
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//40
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INVALID_X_8,
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INVALID_X_8,
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INVALID_X_8,
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};
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const MIPSInstruction tableCop1[32] =
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{
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INSTR("mfc1",&Jit::Comp_mxc1, Dis_mxc1,Int_mxc1, OUT_RT),
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@ -910,7 +908,7 @@ const MIPSInstruction *MIPSGetInstruction(u32 op)
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{
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MipsEncoding encoding = Imme;
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const MIPSInstruction *instr = &tableImmediate[op>>26];
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while (instr->altEncoding != -1)
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while (instr->altEncoding != -1)
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{
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const MIPSInstruction *table = mipsTables[encoding];
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int mask = ((1<<encodingBits[encoding][1])-1);
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@ -927,7 +925,7 @@ const MIPSInstruction *MIPSGetInstruction(u32 op)
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return 0; //invalid instruction
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}
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encoding = (MipsEncoding)instr->altEncoding;
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}
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}
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//alright, we have a valid MIPS instruction!
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return instr;
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}
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@ -944,7 +942,7 @@ void MIPSCompileOp(u32 op)
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{
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if (instr->compile)
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(MIPSComp::jit->*(instr->compile))(op); // woohoo, member functions pointers!
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else
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else
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{
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ERROR_LOG(CPU,"MIPSCompileOp %08x failed",op);
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//MessageBox(0,"ARGH2",0,0);//compile an interpreter call
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