diff --git a/Core/MIPS/IR/IRCompALU.cpp b/Core/MIPS/IR/IRCompALU.cpp
index d68150b178..4a58a02247 100644
--- a/Core/MIPS/IR/IRCompALU.cpp
+++ b/Core/MIPS/IR/IRCompALU.cpp
@@ -292,7 +292,7 @@ void IRJit::Comp_Allegrex2(MIPSOpcode op) {
 		ir.Write(IROp::BSwap16, rd, rt);
 		break;
 	case 0xE0: //wsbw
-		ir.Write(IROp::BSwap16, rd, rt);
+		ir.Write(IROp::BSwap32, rd, rt);
 		break;
 	default:
 		Comp_Generic(op);
diff --git a/Core/MIPS/IR/IRInst.cpp b/Core/MIPS/IR/IRInst.cpp
index 439c0b25fd..b1aaa34abc 100644
--- a/Core/MIPS/IR/IRInst.cpp
+++ b/Core/MIPS/IR/IRInst.cpp
@@ -307,8 +307,11 @@ u32 IRInterpret(MIPSState *mips, const IRInst *inst, const u32 *constPool, int c
 			break;
 		}
 		case IROp::BSwap32:
-			mips->r[inst->dest] = swap32(mips->r[inst->src1]);
+		{
+			u32 x = mips->r[inst->src1];
+			mips->r[inst->dest] = ((x & 0xFF000000) >> 24) | ((x & 0x00FF0000) >> 8) | ((x & 0x0000FF00) << 8) | ((x & 0x000000FF) << 24);
 			break;
+		}
 
 		case IROp::FAdd:
 			mips->f[inst->dest] = mips->f[inst->src1] + mips->f[inst->src2];