From 7ae9c26b6a12b0b0786f5eda570d88afd60a3464 Mon Sep 17 00:00:00 2001 From: Henrik Rydgard Date: Wed, 12 Mar 2014 10:15:09 +0100 Subject: [PATCH] Enable the new vreg flushing mechanism on ARM. Reduce logspam seen in a couple games. --- Core/HLE/sceGe.cpp | 2 +- Core/MIPS/ARM/ArmRegCacheFPU.cpp | 15 ++++++--------- 2 files changed, 7 insertions(+), 10 deletions(-) diff --git a/Core/HLE/sceGe.cpp b/Core/HLE/sceGe.cpp index d77d96d3f2..66506725e6 100644 --- a/Core/HLE/sceGe.cpp +++ b/Core/HLE/sceGe.cpp @@ -152,7 +152,7 @@ public: //if(dl->status < 0 || dl->status > PSP_GE_LIST_PAUSED) // ERROR_LOG(SCEGE, "Weird DL status after signal suspend %x", dl->status); if (newState != PSP_GE_DL_STATE_RUNNING) - INFO_LOG_REPORT(SCEGE, "GE Interrupt: newState might be %d", newState); + DEBUG_LOG_REPORT(SCEGE, "GE Interrupt: newState might be %d", newState); dl->state = PSP_GE_DL_STATE_RUNNING; } diff --git a/Core/MIPS/ARM/ArmRegCacheFPU.cpp b/Core/MIPS/ARM/ArmRegCacheFPU.cpp index 20951d4f8d..b19b628a74 100644 --- a/Core/MIPS/ARM/ArmRegCacheFPU.cpp +++ b/Core/MIPS/ARM/ArmRegCacheFPU.cpp @@ -333,14 +333,12 @@ void ArmRegCacheFPU::FlushAll() { DiscardR(i); } -#if 0 - // Loop through the ARM registers, then use GetMipsRegOffset to determine if MIPS registers are // sequential. This is necessary because we store VFPU registers in a staggered order to get // columns sequential (most VFPU math in nearly all games is in columns, not rows). int numArmRegs; - // We rely on the allocation order being sequental. + // We rely on the allocation order being sequential. const ARMReg baseReg = GetMIPSAllocationOrder(numArmRegs)[0]; for (int i = 0; i < numArmRegs; i++) { @@ -357,6 +355,11 @@ void ArmRegCacheFPU::FlushAll() { if (c == 1) { // ILOG("Got single register: %i (%i)", a, m); emit_->VSTR((ARMReg)(a + S0), CTXREG, GetMipsRegOffset(m)); + } else if (c == 2) { + // Probably not worth using VSTMIA for two. + int offset = GetMipsRegOffset(m); + emit_->VSTR((ARMReg)(a + S0), CTXREG, offset); + emit_->VSTR((ARMReg)(a + 1 + S0), CTXREG, offset + 4); } else { // ILOG("Got sequence: %i at %i (%i)", c, a, m); emit_->ADDI2R(R0, CTXREG, GetMipsRegOffset(m), R1); @@ -382,11 +385,6 @@ void ArmRegCacheFPU::FlushAll() { // already not dirty } } -#else - for (int i = 0; i < NUM_MIPSFPUREG; i++) { - FlushR(i); - } -#endif // Sanity check for (int i = 0; i < numARMFpuReg_; i++) { @@ -428,7 +426,6 @@ void ArmRegCacheFPU::DiscardR(MIPSReg r) { mr[r].spillLock = false; } - bool ArmRegCacheFPU::IsTempX(ARMReg r) const { return ar[r - S0].mipsReg >= TEMP0; }