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samplerjit: Use regcache for linear filtering.
This makes it easier to reuse for mipmap filtering.
This commit is contained in:
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parent
cdf14c8579
commit
6b55d328e5
3 changed files with 174 additions and 91 deletions
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@ -540,7 +540,7 @@ static inline Vec4IntResult SOFTRAST_CALL ApplyTexturing(Sampler::Funcs sampler,
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} else {
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texcolor0 = Vec4<int>(sampler.linear(s, t, x, y, prim_color, tptr0, bufw0, mayHaveMipLevels ? texlevel : 0, mayHaveMipLevels ? frac_texlevel : 0));
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if (mayHaveMipLevels && frac_texlevel) {
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texcolor1 = Vec4<int>(sampler.linear(s, t, x, y, prim_color, tptr0 + 1, bufw0 + 1, texlevel + 1, frac_texlevel));
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texcolor1 = Vec4<int>(sampler.linear(s, t, x, y, prim_color, tptr0 + 1, bufw0 + 1, texlevel + 1, 0));
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}
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}
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@ -73,6 +73,8 @@ private:
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NearestFunc Compile(const SamplerID &id);
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LinearFunc CompileLinear(const SamplerID &id);
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Rasterizer::RegCache::Reg GetZeroVec();
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bool Jit_ReadTextureFormat(const SamplerID &id);
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bool Jit_GetTexData(const SamplerID &id, int bitsPerTexel);
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bool Jit_GetTexDataSwizzled(const SamplerID &id, int bitsPerTexel);
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@ -89,6 +91,7 @@ private:
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bool Jit_PrepareDataOffsets(const SamplerID &id, Rasterizer::RegCache::Reg uReg, Rasterizer::RegCache::Reg vReg);
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bool Jit_PrepareDataDirectOffsets(const SamplerID &id, Rasterizer::RegCache::Reg uReg, Rasterizer::RegCache::Reg vReg, int bitsPerTexel);
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bool Jit_PrepareDataSwizzledOffsets(const SamplerID &id, Rasterizer::RegCache::Reg uReg, Rasterizer::RegCache::Reg vReg, int bitsPerTexel);
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bool Jit_BlendQuad(const SamplerID &id, Rasterizer::RegCache::Reg destReg, bool level1);
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#if PPSSPP_ARCH(ARM64)
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Arm64Gen::ARM64FloatEmitter fp;
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@ -104,6 +107,8 @@ private:
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const u8 *constUNext_ = nullptr;
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const u8 *constVNext_ = nullptr;
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const u8 *constOnes_ = nullptr;
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const u8 *const10Low_ = nullptr;
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const u8 *const10All_ = nullptr;
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std::unordered_map<SamplerID, NearestFunc> cache_;
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std::unordered_map<SamplerID, const u8 *> addresses_;
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@ -162,11 +162,11 @@ LinearFunc SamplerJitCache::CompileLinear(const SamplerID &id) {
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regCache_.Reset(true);
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// Let's drop some helpful constants here.
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const u8 *const10All = AlignCode16();
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const10All_ = AlignCode16();
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Write16(0x10); Write16(0x10); Write16(0x10); Write16(0x10);
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Write16(0x10); Write16(0x10); Write16(0x10); Write16(0x10);
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const u8 *const10Low = AlignCode16();
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const10Low_ = AlignCode16();
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Write16(0x10); Write16(0x10); Write16(0x10); Write16(0x10);
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Write16(0); Write16(0); Write16(0); Write16(0);
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@ -346,7 +346,7 @@ LinearFunc SamplerJitCache::CompileLinear(const SamplerID &id) {
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// This stores the result in an XMM for later processing.
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// We map lookups to nearest CALLs, with arg order: u, v, src, bufw, level
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auto doNearestCall = [&](int off) {
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auto doNearestCall = [&](int off, bool level1) {
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#if PPSSPP_PLATFORM(WINDOWS)
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static const X64Reg uArgReg = RCX;
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static const X64Reg vArgReg = RDX;
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@ -360,30 +360,30 @@ LinearFunc SamplerJitCache::CompileLinear(const SamplerID &id) {
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#endif
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static const X64Reg resultReg = RAX;
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X64Reg uReg = regCache_.Find(RegCache::VEC_ARG_U);
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X64Reg vReg = regCache_.Find(RegCache::VEC_ARG_V);
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X64Reg uReg = regCache_.Find(level1 ? RegCache::VEC_U1 : RegCache::VEC_ARG_U);
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X64Reg vReg = regCache_.Find(level1 ? RegCache::VEC_V1 : RegCache::VEC_ARG_V);
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// Otherwise, we'll overwrite them...
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_assert_(uReg == XMM0 && vReg == XMM1);
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_assert_(level1 || (uReg == XMM0 && vReg == XMM1));
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MOVD_xmm(R(uArgReg), uReg);
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MOVD_xmm(R(vArgReg), vReg);
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X64Reg srcReg = regCache_.Find(RegCache::GEN_ARG_TEXPTR);
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X64Reg bufwReg = regCache_.Find(RegCache::GEN_ARG_BUFW);
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MOV(64, R(srcArgReg), MDisp(srcReg, 0));
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MOV(32, R(bufwArgReg), MDisp(bufwReg, 0));
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MOV(64, R(srcArgReg), MDisp(srcReg, level1 ? 8 : 0));
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MOV(32, R(bufwArgReg), MDisp(bufwReg, level1 ? 4 : 0));
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// Leave level/levelFrac, we just always load from RAM on Windows and lock on POSIX.
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regCache_.Unlock(srcReg, RegCache::GEN_ARG_TEXPTR);
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regCache_.Unlock(bufwReg, RegCache::GEN_ARG_BUFW);
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PSRLDQ(uReg, 4);
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PSRLDQ(vReg, 4);
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regCache_.Unlock(uReg, RegCache::VEC_ARG_U);
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regCache_.Unlock(vReg, RegCache::VEC_ARG_V);
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regCache_.Unlock(uReg, level1 ? RegCache::VEC_U1 : RegCache::VEC_ARG_U);
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regCache_.Unlock(vReg, level1 ? RegCache::VEC_V1 : RegCache::VEC_ARG_V);
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CALL(nearest);
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X64Reg vecResultReg = regCache_.Find(RegCache::VEC_RESULT);
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X64Reg vecResultReg = regCache_.Find(level1 ? RegCache::VEC_RESULT1 : RegCache::VEC_RESULT);
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if (off == 0) {
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MOVD_xmm(vecResultReg, R(resultReg));
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} else {
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@ -393,13 +393,41 @@ LinearFunc SamplerJitCache::CompileLinear(const SamplerID &id) {
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POR(vecResultReg, R(tempReg));
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regCache_.Release(tempReg, RegCache::VEC_TEMP0);
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}
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regCache_.Unlock(vecResultReg, RegCache::VEC_RESULT);
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regCache_.Unlock(vecResultReg, level1 ? RegCache::VEC_RESULT1 : RegCache::VEC_RESULT);
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};
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doNearestCall(0);
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doNearestCall(4);
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doNearestCall(8);
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doNearestCall(12);
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doNearestCall(0, false);
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doNearestCall(4, false);
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doNearestCall(8, false);
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doNearestCall(12, false);
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if (id.hasAnyMips) {
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if (regCache_.Has(RegCache::GEN_ARG_LEVELFRAC)) {
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X64Reg levelFracReg = regCache_.Find(RegCache::GEN_ARG_LEVELFRAC);
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CMP(8, R(levelFracReg), Imm8(0));
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regCache_.Unlock(levelFracReg, RegCache::GEN_ARG_LEVELFRAC);
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} else {
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CMP(8, MDisp(RSP, stackArgPos_ + 24), Imm8(0));
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}
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FixupBranch skip = J_CC(CC_Z, true);
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// Modify the level, so the new level value is used. We don't need the old.
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if (regCache_.Has(RegCache::GEN_ARG_LEVEL)) {
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X64Reg levelReg = regCache_.Find(RegCache::GEN_ARG_LEVEL);
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ADD(32, R(levelReg), Imm8(1));
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regCache_.Unlock(levelReg, RegCache::GEN_ARG_LEVEL);
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} else {
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// It's fine to just modify this in place.
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ADD(32, MDisp(RSP, stackArgPos_ + 16), Imm8(1));
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}
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doNearestCall(0, true);
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doNearestCall(4, true);
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doNearestCall(8, true);
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doNearestCall(12, true);
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SetJumpTarget(skip);
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}
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// We're done with these now.
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regCache_.ForceRelease(RegCache::VEC_ARG_U);
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@ -408,12 +436,27 @@ LinearFunc SamplerJitCache::CompileLinear(const SamplerID &id) {
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regCache_.ForceRelease(RegCache::VEC_U1);
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if (regCache_.Has(RegCache::VEC_V1))
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regCache_.ForceRelease(RegCache::VEC_V1);
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regCache_.ForceRelease(RegCache::VEC_ARG_COLOR);
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regCache_.ForceRelease(RegCache::GEN_ARG_TEXPTR);
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regCache_.ForceRelease(RegCache::GEN_ARG_BUFW);
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if (regCache_.Has(RegCache::GEN_ARG_LEVEL))
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regCache_.ForceRelease(RegCache::GEN_ARG_LEVEL);
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// TODO: Convert to reg cache.
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success = success && Jit_BlendQuad(id, XMM0, false);
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// Last of all, convert to 32-bit channels.
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if (cpu_info.bSSE4_1) {
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PMOVZXWD(XMM0, R(XMM0));
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} else {
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X64Reg zeroReg = GetZeroVec();
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PUNPCKLWD(XMM0, R(zeroReg));
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regCache_.Unlock(zeroReg, RegCache::VEC_ZERO);
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}
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regCache_.ForceRelease(RegCache::VEC_RESULT);
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if (regCache_.Has(RegCache::VEC_RESULT1))
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regCache_.ForceRelease(RegCache::VEC_RESULT1);
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if (!success) {
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regCache_.Reset(false);
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EndWrite();
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@ -421,79 +464,8 @@ LinearFunc SamplerJitCache::CompileLinear(const SamplerID &id) {
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return nullptr;
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}
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// TODO: Convert to reg cache.
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regCache_.ForceRelease(RegCache::VEC_RESULT);
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if (regCache_.Has(RegCache::VEC_RESULT1))
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regCache_.ForceRelease(RegCache::VEC_RESULT1);
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static const X64Reg fpScratchReg1 = XMM1;
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static const X64Reg fpScratchReg2 = XMM2;
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static const X64Reg fpScratchReg3 = XMM3;
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static const X64Reg fpScratchReg4 = XMM4;
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static const X64Reg fpScratchReg5 = XMM5;
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// First put the top RRRRRRRR LLLLLLLL into fpScratchReg1, bottom into fpScratchReg2.
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// Start with XXXX XXXX RRRR LLLL, and then expand 8 bits to 16 bits.
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if (!cpu_info.bSSE4_1) {
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PXOR(fpScratchReg3, R(fpScratchReg3));
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PSHUFD(fpScratchReg1, R(XMM5), _MM_SHUFFLE(0, 0, 1, 0));
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PSHUFD(fpScratchReg2, R(XMM5), _MM_SHUFFLE(0, 0, 3, 2));
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PUNPCKLBW(fpScratchReg1, R(fpScratchReg3));
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PUNPCKLBW(fpScratchReg2, R(fpScratchReg3));
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} else {
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PSHUFD(fpScratchReg2, R(XMM5), _MM_SHUFFLE(0, 0, 3, 2));
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PMOVZXBW(fpScratchReg1, R(XMM5));
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PMOVZXBW(fpScratchReg2, R(fpScratchReg2));
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}
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// Grab frac_u and spread to lower (L) lanes.
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X64Reg fracUReg = regCache_.Find(RegCache::GEN_ARG_FRAC_U);
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MOVD_xmm(fpScratchReg5, R(fracUReg));
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regCache_.Unlock(fracUReg, RegCache::GEN_ARG_FRAC_U);
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regCache_.ForceRelease(RegCache::GEN_ARG_FRAC_U);
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PSHUFLW(fpScratchReg5, R(fpScratchReg5), _MM_SHUFFLE(0, 0, 0, 0));
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// Now subtract 0x10 - frac_u in the L lanes only: 00000000 LLLLLLLL.
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MOVDQA(fpScratchReg3, M(const10Low));
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PSUBW(fpScratchReg3, R(fpScratchReg5));
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// Then we just shift and OR in the original frac_u.
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PSLLDQ(fpScratchReg5, 8);
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POR(fpScratchReg3, R(fpScratchReg5));
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// Okay, we have 8-bits in the top and bottom rows for the color.
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// Multiply by frac to get 12, which we keep for the next stage.
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PMULLW(fpScratchReg1, R(fpScratchReg3));
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PMULLW(fpScratchReg2, R(fpScratchReg3));
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// Time for frac_v. This time, we want it in all 8 lanes.
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X64Reg fracVReg = regCache_.Find(RegCache::GEN_ARG_FRAC_V);
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MOVD_xmm(fpScratchReg5, R(fracVReg));
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regCache_.Unlock(fracVReg, RegCache::GEN_ARG_FRAC_V);
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regCache_.ForceRelease(RegCache::GEN_ARG_FRAC_V);
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PSHUFLW(fpScratchReg5, R(fpScratchReg5), _MM_SHUFFLE(0, 0, 0, 0));
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PSHUFD(fpScratchReg5, R(fpScratchReg5), _MM_SHUFFLE(0, 0, 0, 0));
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// Now, inverse fpScratchReg5 into fpScratchReg3 for the top row.
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MOVDQA(fpScratchReg3, M(const10All));
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PSUBW(fpScratchReg3, R(fpScratchReg5));
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// We had 12, plus 4 frac, that gives us 16.
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PMULLW(fpScratchReg2, R(fpScratchReg5));
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PMULLW(fpScratchReg1, R(fpScratchReg3));
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// Finally, time to sum them all up and divide by 256 to get back to 8 bits.
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PADDUSW(fpScratchReg2, R(fpScratchReg1));
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PSHUFD(XMM0, R(fpScratchReg2), _MM_SHUFFLE(3, 2, 3, 2));
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PADDUSW(XMM0, R(fpScratchReg2));
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PSRLW(XMM0, 8);
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// Last of all, convert to 32-bit channels.
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if (cpu_info.bSSE4_1) {
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PMOVZXWD(XMM0, R(XMM0));
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} else {
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PXOR(fpScratchReg1, R(fpScratchReg1));
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PUNPCKLWD(XMM0, R(fpScratchReg1));
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}
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// TODO: Actually use this (and color) at some point.
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// TODO: Actually use these at some point.
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regCache_.ForceRelease(RegCache::VEC_ARG_COLOR);
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if (regCache_.Has(RegCache::GEN_ARG_LEVELFRAC))
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regCache_.ForceRelease(RegCache::GEN_ARG_LEVELFRAC);
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@ -521,6 +493,112 @@ LinearFunc SamplerJitCache::CompileLinear(const SamplerID &id) {
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return (LinearFunc)start;
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}
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RegCache::Reg SamplerJitCache::GetZeroVec() {
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if (!regCache_.Has(RegCache::VEC_ZERO)) {
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X64Reg r = regCache_.Alloc(RegCache::VEC_ZERO);
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PXOR(r, R(r));
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return r;
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}
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return regCache_.Find(RegCache::VEC_ZERO);
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}
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bool SamplerJitCache::Jit_BlendQuad(const SamplerID &id, Rasterizer::RegCache::Reg destReg, bool level1) {
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// First put the top RRRRRRRR LLLLLLLL into topReg, bottom into bottomReg.
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// Start with XXXX XXXX RRRR LLLL, and then expand 8 bits to 16 bits.
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X64Reg topReg = regCache_.Alloc(RegCache::VEC_TEMP0);
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X64Reg bottomReg = regCache_.Alloc(RegCache::VEC_TEMP1);
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X64Reg quadReg = regCache_.Find(level1 ? RegCache::VEC_RESULT1 : RegCache::VEC_RESULT);
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if (!cpu_info.bSSE4_1) {
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X64Reg zeroReg = GetZeroVec();
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PSHUFD(topReg, R(quadReg), _MM_SHUFFLE(0, 0, 1, 0));
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PSHUFD(bottomReg, R(quadReg), _MM_SHUFFLE(0, 0, 3, 2));
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PUNPCKLBW(topReg, R(zeroReg));
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PUNPCKLBW(bottomReg, R(zeroReg));
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regCache_.Unlock(zeroReg, RegCache::VEC_ZERO);
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} else {
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PSHUFD(bottomReg, R(quadReg), _MM_SHUFFLE(0, 0, 3, 2));
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PMOVZXBW(topReg, R(quadReg));
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PMOVZXBW(bottomReg, R(bottomReg));
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}
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regCache_.Unlock(quadReg, level1 ? RegCache::VEC_RESULT1 : RegCache::VEC_RESULT);
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regCache_.ForceRelease(level1 ? RegCache::VEC_RESULT1 : RegCache::VEC_RESULT);
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// Grab frac_u and spread to lower (L) lanes.
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X64Reg fracReg = regCache_.Alloc(RegCache::VEC_TEMP2);
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X64Reg fracMulReg = regCache_.Alloc(RegCache::VEC_TEMP3);
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if (level1) {
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MOVD_xmm(fracReg, MDisp(RSP, stackArgPos_ + stackFracUV1Offset_));
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} else {
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X64Reg fracUReg = regCache_.Find(RegCache::GEN_ARG_FRAC_U);
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MOVD_xmm(fracReg, R(fracUReg));
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regCache_.Unlock(fracUReg, RegCache::GEN_ARG_FRAC_U);
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regCache_.ForceRelease(RegCache::GEN_ARG_FRAC_U);
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}
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PSHUFLW(fracReg, R(fracReg), _MM_SHUFFLE(0, 0, 0, 0));
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// Now subtract 0x10 - frac_u in the L lanes only: 00000000 LLLLLLLL.
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MOVDQA(fracMulReg, M(const10Low_));
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PSUBW(fracMulReg, R(fracReg));
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// Then we just shift and OR in the original frac_u.
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PSLLDQ(fracReg, 8);
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POR(fracMulReg, R(fracReg));
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regCache_.Release(fracReg, RegCache::VEC_TEMP2);
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// Okay, we have 8-bits in the top and bottom rows for the color.
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// Multiply by frac to get 12, which we keep for the next stage.
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PMULLW(topReg, R(fracMulReg));
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PMULLW(bottomReg, R(fracMulReg));
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regCache_.Release(fracMulReg, RegCache::VEC_TEMP3);
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// Time for frac_v. This time, we want it in all 8 lanes.
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fracReg = regCache_.Alloc(RegCache::VEC_TEMP2);
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X64Reg fracTopReg = regCache_.Alloc(RegCache::VEC_TEMP3);
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if (level1) {
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MOVD_xmm(fracReg, MDisp(RSP, stackArgPos_ + stackFracUV1Offset_ + 4));
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} else {
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X64Reg fracVReg = regCache_.Find(RegCache::GEN_ARG_FRAC_V);
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MOVD_xmm(fracReg, R(fracVReg));
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regCache_.Unlock(fracVReg, RegCache::GEN_ARG_FRAC_V);
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regCache_.ForceRelease(RegCache::GEN_ARG_FRAC_V);
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}
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PSHUFLW(fracReg, R(fracReg), _MM_SHUFFLE(0, 0, 0, 0));
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PSHUFD(fracReg, R(fracReg), _MM_SHUFFLE(0, 0, 0, 0));
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// Now, inverse fracReg into fracTopReg for the top row.
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MOVDQA(fracTopReg, M(const10All_));
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PSUBW(fracTopReg, R(fracReg));
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// We had 12, plus 4 frac, that gives us 16.
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PMULLW(bottomReg, R(fracReg));
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PMULLW(topReg, R(fracTopReg));
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regCache_.Release(fracReg, RegCache::VEC_TEMP2);
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regCache_.Release(fracTopReg, RegCache::VEC_TEMP3);
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// Finally, time to sum them all up and divide by 256 to get back to 8 bits.
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PADDUSW(bottomReg, R(topReg));
|
||||
regCache_.Release(topReg, RegCache::VEC_TEMP0);
|
||||
bool success = regCache_.ChangeReg(destReg, level1 ? RegCache::VEC_RESULT1 : RegCache::VEC_RESULT);
|
||||
if (!success) {
|
||||
_assert_msg_(destReg == bottomReg, "Unexpected other reg locked as destReg");
|
||||
X64Reg otherReg = regCache_.Alloc(RegCache::VEC_TEMP0);
|
||||
PSHUFD(otherReg, R(bottomReg), _MM_SHUFFLE(3, 2, 3, 2));
|
||||
PADDUSW(bottomReg, R(otherReg));
|
||||
regCache_.Release(otherReg, RegCache::VEC_TEMP0);
|
||||
regCache_.Release(bottomReg, RegCache::VEC_TEMP1);
|
||||
|
||||
// Okay, now it can be changed.
|
||||
regCache_.ChangeReg(destReg, level1 ? RegCache::VEC_RESULT1 : RegCache::VEC_RESULT);
|
||||
} else {
|
||||
PSHUFD(destReg, R(bottomReg), _MM_SHUFFLE(3, 2, 3, 2));
|
||||
PADDUSW(destReg, R(bottomReg));
|
||||
regCache_.Release(bottomReg, RegCache::VEC_TEMP1);
|
||||
}
|
||||
|
||||
PSRLW(destReg, 8);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool SamplerJitCache::Jit_ReadTextureFormat(const SamplerID &id) {
|
||||
GETextureFormat fmt = id.TexFmt();
|
||||
bool success = true;
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue