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https://github.com/hrydgard/ppsspp.git
synced 2025-04-02 11:01:50 -04:00
ARM32: Remove a lot of non-NEON fallback paths
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parent
19261c6c49
commit
584e94f01e
10 changed files with 339 additions and 910 deletions
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@ -1,14 +1,12 @@
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#include "ppsspp_config.h"
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#include "fast_math.h"
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#include "fast_matrix.h"
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void InitFastMath(int enableNEON) {
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// Every architecture has its own define. This needs to be added to.
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if (enableNEON) {
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void InitFastMath() {
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#ifndef _MSC_VER
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#if PPSSPP_ARCH(ARM_NEON) && !PPSSPP_ARCH(ARM64)
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fast_matrix_mul_4x4 = &fast_matrix_mul_4x4_neon;
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#endif
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#endif
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}
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}
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@ -14,7 +14,7 @@ extern "C" {
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// See fast_matrix.h for the first set of functions.
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void InitFastMath(int enableNEON);
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void InitFastMath();
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#ifdef __cplusplus
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}
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@ -138,9 +138,7 @@ void ArmJit::GenerateFixedCode() {
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// consumed by CALL.
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SUB(R_SP, R_SP, 4);
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// Now we are correctly aligned and plan to stay that way.
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if (cpu_info.bNEON) {
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VPUSH(D8, 8);
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}
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VPUSH(D8, 8);
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// Fixed registers, these are always kept when in Jit context.
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// R8 is used to hold flags during delay slots. Not always needed.
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@ -244,10 +242,7 @@ void ArmJit::GenerateFixedCode() {
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SaveDowncount();
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RestoreRoundingMode(true);
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// Doing this above the downcount for better pipelining (slightly.)
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if (cpu_info.bNEON) {
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VPOP(D8, 8);
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}
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VPOP(D8, 8);
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ADD(R_SP, R_SP, 4);
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@ -1132,10 +1132,6 @@ namespace MIPSComp
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DISABLE;
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}
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if (!cpu_info.bNEON) {
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DISABLE;
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}
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// This multi-VCVT.F32.F16 is only available in the VFPv4 extension.
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// The VFPv3 one is VCVTB, VCVTT which we don't yet have support for.
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if (!(cpu_info.bHalf && cpu_info.bVFPv4)) {
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@ -1599,10 +1595,6 @@ namespace MIPSComp
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DISABLE;
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}
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if (!cpu_info.bNEON) {
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DISABLE;
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}
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int bits = ((op >> 16) & 2) == 0 ? 8 : 16; // vi2uc/vi2c (0/1), vi2us/vi2s (2/3)
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bool unsignedOp = ((op >> 16) & 1) == 0; // vi2uc (0), vi2us (2)
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@ -27,13 +27,7 @@
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using namespace ArmGen;
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using namespace ArmJitConstants;
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ArmRegCacheFPU::ArmRegCacheFPU(MIPSState *mipsState, MIPSComp::JitState *js, MIPSComp::JitOptions *jo) : mips_(mipsState), js_(js), jo_(jo), vr(mr + 32) {
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if (cpu_info.bNEON) {
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numARMFpuReg_ = 32;
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} else {
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numARMFpuReg_ = 16;
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}
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}
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ArmRegCacheFPU::ArmRegCacheFPU(MIPSState *mipsState, MIPSComp::JitState *js, MIPSComp::JitOptions *jo) : mips_(mipsState), js_(js), jo_(jo), vr(mr + 32) {}
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void ArmRegCacheFPU::Start(MIPSAnalyst::AnalysisResults &stats) {
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if (!initialReady) {
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@ -47,7 +41,7 @@ void ArmRegCacheFPU::Start(MIPSAnalyst::AnalysisResults &stats) {
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}
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void ArmRegCacheFPU::SetupInitialRegs() {
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for (int i = 0; i < numARMFpuReg_; i++) {
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for (int i = 0; i < NUM_ARMFPUREG; i++) {
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arInitial[i].mipsReg = -1;
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arInitial[i].isDirty = false;
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}
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@ -57,7 +51,7 @@ void ArmRegCacheFPU::SetupInitialRegs() {
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mrInitial[i].spillLock = false;
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mrInitial[i].tempLock = false;
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}
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for (int i = 0; i < MAX_ARMQUADS; i++) {
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for (int i = 0; i < NUM_ARMQUADS; i++) {
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qr[i].isDirty = false;
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qr[i].mipsVec = -1;
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qr[i].sz = V_Invalid;
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@ -68,14 +62,6 @@ void ArmRegCacheFPU::SetupInitialRegs() {
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}
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const ARMReg *ArmRegCacheFPU::GetMIPSAllocationOrder(int &count) {
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// We reserve S0-S1 as scratch. Can afford two registers. Maybe even four, which could simplify some things.
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static const ARMReg allocationOrder[] = {
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S2, S3,
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S4, S5, S6, S7,
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S8, S9, S10, S11,
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S12, S13, S14, S15
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};
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// VFP mapping
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// VFPU registers and regular FP registers are mapped interchangably on top of the standard
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// 16 FPU registers.
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@ -116,12 +102,9 @@ const ARMReg *ArmRegCacheFPU::GetMIPSAllocationOrder(int &count) {
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if (jo_->useNEONVFPU) {
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count = sizeof(allocationOrderNEONVFPU) / sizeof(const ARMReg);
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return allocationOrderNEONVFPU;
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} else if (cpu_info.bNEON) {
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} else {
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count = sizeof(allocationOrderNEON) / sizeof(const ARMReg);
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return allocationOrderNEON;
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} else {
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count = sizeof(allocationOrder) / sizeof(const ARMReg);
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return allocationOrder;
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}
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}
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@ -404,19 +387,12 @@ void ArmRegCacheFPU::FlushR(MIPSReg r) {
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mr[r].reg = (int)INVALID_REG;
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}
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int ArmRegCacheFPU::GetNumARMFPURegs() {
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if (cpu_info.bNEON)
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return 32;
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else
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return 16;
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}
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// Scalar only. Need a similar one for sequential Q vectors.
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int ArmRegCacheFPU::FlushGetSequential(int a, int maxArmReg) {
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int ArmRegCacheFPU::FlushGetSequential(int a) {
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int c = 1;
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int lastMipsOffset = GetMipsRegOffset(ar[a].mipsReg);
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a++;
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while (a < maxArmReg) {
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while (a < 32) {
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if (!ar[a].isDirty || ar[a].mipsReg == -1)
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break;
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int mipsOffset = GetMipsRegOffset(ar[a].mipsReg);
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@ -444,7 +420,7 @@ void ArmRegCacheFPU::FlushAll() {
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// Flush quads!
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// These could also use sequential detection.
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for (int i = 4; i < MAX_ARMQUADS; i++) {
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for (int i = 4; i < NUM_ARMQUADS; i++) {
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QFlush(i);
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}
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@ -466,7 +442,7 @@ void ArmRegCacheFPU::FlushAll() {
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continue;
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}
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int c = FlushGetSequential(a, GetNumARMFPURegs());
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int c = FlushGetSequential(a);
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if (c == 1) {
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// INFO_LOG(JIT, "Got single register: %i (%i)", a, m);
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emit_->VSTR((ARMReg)(a + S0), CTXREG, GetMipsRegOffset(m));
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@ -502,7 +478,7 @@ void ArmRegCacheFPU::FlushAll() {
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}
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// Sanity check
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for (int i = 0; i < numARMFpuReg_; i++) {
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for (int i = 0; i < NUM_ARMFPUREG; i++) {
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if (ar[i].mipsReg != -1) {
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ERROR_LOG(JIT, "Flush fail: ar[%i].mipsReg=%i", i, ar[i].mipsReg);
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}
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@ -594,7 +570,7 @@ void ArmRegCacheFPU::ReleaseSpillLocksAndDiscardTemps() {
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for (int i = TEMP0; i < TEMP0 + NUM_TEMPS; ++i) {
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DiscardR(i);
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}
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for (int i = 0; i < MAX_ARMQUADS; i++) {
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for (int i = 0; i < NUM_ARMQUADS; i++) {
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qr[i].spillLock = false;
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if (qr[i].isTemp) {
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qr[i].isTemp = false;
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@ -127,7 +127,7 @@ public:
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// VFPU registers as single VFP registers.
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ArmGen::ARMReg V(int vreg) { return R(vreg + 32); }
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int FlushGetSequential(int a, int maxArmReg);
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int FlushGetSequential(int a);
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void FlushAll();
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// This one is allowed at any point.
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@ -180,7 +180,6 @@ private:
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}
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// This one WILL get a free quad as long as you haven't spill-locked them all.
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int QGetFreeQuad(int start, int count, const char *reason);
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int GetNumARMFPURegs();
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void SetupInitialRegs();
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@ -189,24 +188,23 @@ private:
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MIPSComp::JitState *js_;
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MIPSComp::JitOptions *jo_;
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int numARMFpuReg_;
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int qTime_;
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enum {
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// With NEON, we have 64 S = 32 D = 16 Q registers. Only the first 32 S registers
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// are individually mappable though.
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MAX_ARMFPUREG = 32,
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MAX_ARMQUADS = 16,
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NUM_ARMFPUREG = 32,
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NUM_ARMQUADS = 16,
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NUM_MIPSFPUREG = ArmJitConstants::TOTAL_MAPPABLE_MIPSFPUREGS,
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};
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FPURegARM ar[MAX_ARMFPUREG];
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FPURegARM ar[NUM_ARMFPUREG];
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FPURegMIPS mr[NUM_MIPSFPUREG];
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FPURegQuad qr[MAX_ARMQUADS];
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FPURegQuad qr[NUM_ARMQUADS];
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FPURegMIPS *vr;
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bool pendingFlush;
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bool initialReady = false;
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FPURegARM arInitial[MAX_ARMFPUREG];
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FPURegARM arInitial[NUM_ARMFPUREG];
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FPURegMIPS mrInitial[NUM_MIPSFPUREG];
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};
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@ -38,7 +38,7 @@ namespace MIPSComp {
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// ARM only
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downcountInRegister = true;
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useNEONVFPU = false; // true
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if (!cpu_info.bNEON || Disabled(JitDisable::SIMD))
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if (Disabled(JitDisable::SIMD))
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useNEONVFPU = false;
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//ARM64
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@ -901,9 +901,7 @@ CheckAlphaResult CheckAlphaRGBA8888Basic(const u32 *pixelData, int stride, int w
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#ifdef _M_SSE
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return CheckAlphaRGBA8888SSE2(pixelData, stride, w, h);
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#elif PPSSPP_ARCH(ARM_NEON)
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if (cpu_info.bNEON) {
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return CheckAlphaRGBA8888NEON(pixelData, stride, w, h);
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}
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return CheckAlphaRGBA8888NEON(pixelData, stride, w, h);
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#endif
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}
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@ -931,9 +929,7 @@ CheckAlphaResult CheckAlphaABGR4444Basic(const u32 *pixelData, int stride, int w
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#ifdef _M_SSE
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return CheckAlphaABGR4444SSE2(pixelData, stride, w, h);
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#elif PPSSPP_ARCH(ARM_NEON)
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if (cpu_info.bNEON) {
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return CheckAlphaABGR4444NEON(pixelData, stride, w, h);
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}
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return CheckAlphaABGR4444NEON(pixelData, stride, w, h);
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#endif
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}
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#ifdef _M_SSE
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return CheckAlphaABGR1555SSE2(pixelData, stride, w, h);
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#elif PPSSPP_ARCH(ARM_NEON)
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if (cpu_info.bNEON) {
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return CheckAlphaABGR1555NEON(pixelData, stride, w, h);
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}
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return CheckAlphaABGR1555NEON(pixelData, stride, w, h);
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#endif
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}
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@ -996,9 +990,7 @@ CheckAlphaResult CheckAlphaRGBA4444Basic(const u32 *pixelData, int stride, int w
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#ifdef _M_SSE
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return CheckAlphaRGBA4444SSE2(pixelData, stride, w, h);
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#elif PPSSPP_ARCH(ARM_NEON)
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if (cpu_info.bNEON) {
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return CheckAlphaRGBA4444NEON(pixelData, stride, w, h);
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}
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return CheckAlphaRGBA4444NEON(pixelData, stride, w, h);
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#endif
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}
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@ -1029,9 +1021,7 @@ CheckAlphaResult CheckAlphaRGBA5551Basic(const u32 *pixelData, int stride, int w
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#ifdef _M_SSE
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return CheckAlphaRGBA5551SSE2(pixelData, stride, w, h);
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#elif PPSSPP_ARCH(ARM_NEON)
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if (cpu_info.bNEON) {
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return CheckAlphaRGBA5551NEON(pixelData, stride, w, h);
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}
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return CheckAlphaRGBA5551NEON(pixelData, stride, w, h);
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#endif
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}
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File diff suppressed because it is too large
Load diff
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@ -464,7 +464,7 @@ void NativeInit(int argc, const char *argv[], const char *savegame_dir, const ch
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ShaderTranslationInit();
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InitFastMath(cpu_info.bNEON);
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InitFastMath();
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g_threadManager.Init(cpu_info.num_cores, cpu_info.logical_cpu_count);
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g_Discord.SetPresenceMenu();
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