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Simplify some MIPS table flags.

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Unknown W. Brackets 2013-08-11 17:02:00 -07:00
parent ebfa3de388
commit 4ebf355ece
2 changed files with 9 additions and 14 deletions
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14
Core/MIPS/MIPSAnalyst.cpp
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@ -54,7 +54,7 @@ namespace MIPSAnalyst
if (MIPS_GET_RT(opinfo) == reg) if (MIPS_GET_RT(opinfo) == reg)
return true; return true;
} }
if (opinfo & (IN_RS | IN_RS_ADDR | IN_RS_SHIFT)) if (opinfo & IN_RS)
{ {
if (MIPS_GET_RS(opinfo) == reg) if (MIPS_GET_RS(opinfo) == reg)
return true; return true;
@ -190,8 +190,7 @@ namespace MIPSAnalyst
int rd = MIPS_GET_RD(op); int rd = MIPS_GET_RD(op);
if ( if (
((info & IN_RS) && (rs == reg)) || ((info & IN_RS) && !(info & IN_RS_ADDR) && (rs == reg)) ||
((info & IN_RS_SHIFT) && (rs == reg)) ||
((info & IN_RT) && (rt == reg))) ((info & IN_RT) && (rt == reg)))
{ {
if (regAnal[reg].firstRead == -1) if (regAnal[reg].firstRead == -1)
@ -293,13 +292,7 @@ namespace MIPSAnalyst
u32 op = Memory::Read_Instruction(addr); u32 op = Memory::Read_Instruction(addr);
u32 info = MIPSGetInfo(op); u32 info = MIPSGetInfo(op);
if ( if ((info & IN_RS) && (MIPS_GET_RS(op) == reg))
((info & IN_RS) ||
(info & IN_RS_SHIFT) ||
(info & IN_RS_ADDR))
&&
(MIPS_GET_RS(op) == reg)
)
return true; return true;
if ((info & IN_RT) && (MIPS_GET_RT(op) == reg)) if ((info & IN_RT) && (MIPS_GET_RT(op) == reg))
return true; return true;
@ -644,6 +637,7 @@ namespace MIPSAnalyst
info.dataSize = 2; info.dataSize = 2;
break; break;
case MEMTYPE_WORD: case MEMTYPE_WORD:
case MEMTYPE_FLOAT:
info.dataSize = 4; info.dataSize = 4;
break; break;
} }

9
Core/MIPS/MIPSTables.h
View file

@ -30,10 +30,11 @@
// as long as the other flags are checked, // as long as the other flags are checked,
// there is no way to misinterprete these // there is no way to misinterprete these
// as CONDTYPE_X // as CONDTYPE_X
#define MEMTYPE_MASK 0x00000003 #define MEMTYPE_MASK 0x00000007
#define MEMTYPE_BYTE 0x00000001 #define MEMTYPE_BYTE 0x00000001
#define MEMTYPE_HWORD 0x00000002 #define MEMTYPE_HWORD 0x00000002
#define MEMTYPE_WORD 0x00000003 #define MEMTYPE_WORD 0x00000003
#define MEMTYPE_FLOAT 0x00000004
#define IS_CONDMOVE 0x00000008 #define IS_CONDMOVE 0x00000008
#define DELAYSLOT 0x00000010 #define DELAYSLOT 0x00000010
@ -43,9 +44,9 @@
#define IS_CONDBRANCH 0x00000100 #define IS_CONDBRANCH 0x00000100
#define IS_JUMP 0x00000200 #define IS_JUMP 0x00000200
#define IN_RS_SHIFT 0x00000400 #define IN_RS 0x00000400
#define IN_RS_ADDR 0x00000800 #define IN_RS_ADDR (0x00000800 | IN_RS)
#define IN_RS 0x00001000 #define IN_RS_SHIFT (0x00001000 | IN_RS)
#define IN_RT 0x00002000 #define IN_RT 0x00002000
#define IN_SA 0x00004000 #define IN_SA 0x00004000
#define IN_IMM16 0x00008000 #define IN_IMM16 0x00008000